This register is used to control the peripherals connected to dedicated IO pin 6
Only reset by a cold reset (ignores warm reset).
NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance | Base Address | Register Address |
---|---|---|
i_io48_pin_mux_dedicated_io_grp | 0xFFD07200 | 0xFFD07214 |
Offset: 0x14
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
sel RW 0xF |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:4 | Reserved | Reserved |
RO | 0x0 |
3:0 | sel | Select peripheral signals connected Dedicated IO 6 0000 (0) Pin is connected to Peripheral signal not applicable 0001 (1) Pin is connected to Peripheral signal not applicable 0010 (2) Pin is connected to Peripheral signal not applicable 0011 (3) Pin is connected to Peripheral signal not applicable 0100 (4) Pin is connected to Peripheral signal qspi.ss0 0101 (5) Pin is connected to Peripheral signal not applicable 0110 (6) Pin is connected to Peripheral signal not applicable 0111 (7) Pin is connected to Peripheral signal not applicable 1000 (8) Pin is connected to Peripheral signal sdmmc.cclk 1001 (9) Pin is connected to Peripheral signal not applicable 1010 (10) Pin is connected to Peripheral signal not applicable 1011 (11) Pin is connected to Peripheral signal not applicable 1100 (12) Pin is connected to Peripheral signal not applicable 1101 (13) Pin is connected to Peripheral signal not applicable 1110 (14) Pin is connected to Peripheral signal nand.we_n 1111 (15) Pin is connected to Peripheral signal gpio2.io2 |
RW | 0xF |