dramodt0

         
      
Module Instance Base Address Register Address
i_io48_hmc_mmr_io48_mmr 0xFFCFA000 0xFFCFA054

Offset: 0x54

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_read_odt_chip

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_write_odt_chip

0x0

dramodt0 Fields

Bit Name Description Access Reset
31:16 cfg_read_odt_chip
ODT scheme setting for read command. Setting seperated into 4 sections: [CS3][CS2][CS1][CS0] Each section consists of 4 bits to indicate which chip should ODT be asserted when write occurs on current CS. Eg: if we set to 16
RW 0x0
15:0 cfg_write_odt_chip
ODT scheme setting for write command. Setting seperated into 4 sections: [CS3][CS2][CS1][CS0] Each section consists of 4 bits to indicate which chip should ODT be asserted when write occurs on current CS. Eg: if we set to 16
RW 0x0