Module Instance | Base Address | Register Address |
---|---|---|
i_io48_hmc_mmr_io48_mmr | 0xFFCFA000 | 0xFFCFA074 |
Offset: 0x74
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
cfg_t_param_dqstrk_to_valid 0x0 |
cfg_t_param_dqstrk_to_valid_last 0x0 |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
cfg_period_dqstrk_interval 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:24 | cfg_t_param_dqstrk_to_valid | DQS Tracking Rd to Valid timing for Ranks other than the Last |
RW | 0x0 |
23:16 | cfg_t_param_dqstrk_to_valid_last | DQS Tracking Rd to Valid timing for the last Rank |
RW | 0x0 |
15:0 | cfg_period_dqstrk_interval | Inverval between two controller controlled periodic DQS tracking |
RW | 0x0 |