Module Instance | Base Address | Register Address |
---|---|---|
i_io48_hmc_mmr_io48_mmr | 0xFFCFA000 | 0xFFCFA0E0 |
Offset: 0xE0
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
mr_cmd_opcode 0x0 |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
mr_cmd_opcode 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:0 | mr_cmd_opcode | [31:27] reserved. Register Command Opcode Information to be used for Register Command Reserved [31:10] falling edge CA. [9:0] rising edge CA DDR4 [26:24] C2:C0 [23] ACT [22:21] BG1:BG0 [20] Reserved [19:18] BA1:BA0 [17] A17 [16] RAS [15] CAS [14] WE [13:0] A13:A0 DDR3 [26:21] Reserved [20:18] BA2:BA0 [17] A17 [16] RAS [15] CAS [14] WE [13] Reserved [12:0] A12:A0 RLDRAM3 [26] Reserved [25:22] BA3:BA0 [21] REF [20] WE [19:0] A19:A0 |
RW | 0x0 |