caltiming1

         
      
Module Instance Base Address Register Address
i_io48_hmc_mmr_io48_mmr 0xFFCFA000 0xFFCFA080

Offset: 0x80

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_rd_to_wr_diff_chip

0x0

cfg_t_param_rd_to_wr

0x0

cfg_t_param_rd_to_rd_diff_bg

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_rd_to_rd_diff_bg

0x0

cfg_t_param_rd_to_rd_diff_chip

0x0

cfg_t_param_rd_to_rd

0x0

caltiming1 Fields

Bit Name Description Access Reset
29:24 cfg_t_param_rd_to_wr_diff_chip
Read to write command timing on different chips
RW 0x0
23:18 cfg_t_param_rd_to_wr
Write to read command timing on same bank
RW 0x0
17:12 cfg_t_param_rd_to_rd_diff_bg
Read to read command timing on different chips
RW 0x0
11:6 cfg_t_param_rd_to_rd_diff_chip
Read to read command timing on different chips
RW 0x0
5:0 cfg_t_param_rd_to_rd
Read to read command timing on same bank
RW 0x0