Controls the L3 master ARCACHE and AWCACHE AXI signals.
These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation
All fields are reset by a cold or warm reset.
Module Instance | Base Address | Register Address |
---|---|---|
i_sys_mgr_core | 0xFFD06000 | 0xFFD06040 |
Offset: 0x40
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
ptp_clk_sel RW 0x0 |
Bit | Name | Description | Access | Reset | ||||||
---|---|---|---|---|---|---|---|---|---|---|
0 | ptp_clk_sel | Selects the source of the PTP reference clock between emac_ptp_clk from the Clock Manager or f2s_ptp_ref_clk from the FPGA Fabric.
|
RW | 0x0 |