These free resources are available to the Intel® Developer Network for PCI Express* Architecture community.

PCI Express* (PCIe) Specifications

Root Complex IDE Key Configuration Unit - Software Programming Guide defines the Intel Root Port register programming interface for configuring PCI Express* (PCIe*) Integrity and Data Encryption (IDE) and Compute Express Link (CXL) Integrity and Data Encryption (IDE) capabilities. Send your feedback to

The PHY Interface for the PCI Express* (PIPE) Architecture Revision 6.2.1 is an updated version of the PIPE spec that supports PCI Express*, SATA, USB3.2, DisplayPort, and USB4 Architectures.

The Logical PHY Interface Specification, Revision 1.1 defines the interface between the link layer and the logical physical layer for PCI Express* and CXL architectures.

The LPIF Adapter for Die-to-Die Interconnect Revision 0.5 outlines implementation guidelines for using the Logical PHY Interface (LPIF) for die-to-die transport.

2-Wire Translator Component Spec DRAFT Revision 0.3 defines a component solution for PCI-Express forward/backward compatibility of the sideband bus (SMBus/I3C).

The PCI Express* Device Security Enhancements Specification is deprecated and is not recommended for new implementations. Instead, please refer to the Security Protocol and Data Model (SPDM) Specification ( and Component Measurement and Authentication (CMA) & Data Object Exchange (DOE) ECNs (

PCI Express* Resources

If you're new to PCI Express*, check out content from the PCI-SIG*.
Read the PDF (744 KB) ›

Compute Express Link™ (CXL) Resources

CXL-cache/mem Protocol Interface (CPI) specification, has been developed to map coherent protocols between an agent and a fabric.

Streaming Fabric Interface (SFI) Specification has been developed to map Load/Store protocols (like PCIe) between an agent and a fabric.

CXL Memory Device SW Guide describes how System Firmware, OS and UEFI may configure CXL Type 3 devices.