Intel® eASIC™ Devices
Intel® eASIC™ devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs. These devices provide lower unit-cost and lower power compared to FPGAs and faster time to market and lower non-recurring engineering cost compared to standard-cell ASICs. The new Intel® eASIC™ N5X devices, formerly codenamed Diamond Mesa, add a hard processor system and secure device managers compatible with Intel® FPGAs to extend Intel's logic portfolio offerings.
Intel® eASIC™ Devices
Benefits
Lower Power and Unit Cost
Provides unit-cost and power reductions compared to FPGA by replacing SRAM configuration logic with patented single-via customization technology and disconnecting power from unused device structures.
Time Advantage
Faster time to market and turnaround time than traditional ASICs due to simplified design flow, customization of only a few mask layers, and when feasible no PCB change from base FPGA designs.
High Performance
The structured ASIC combines logic, memory, DSP functionality, high-speed memory interfaces, and high-speed transceivers for high-performance data plane or control plane applications.
Broad IP Support
A wealth of fully verified eASIC-ready IP cores from Intel and third-party alliance partners.
Simplified Design Flow
Intel® eASIC™ device eTools offer a framework for design conversion and validation using a combination of internally developed and industry standard third-party tools.
Market Applicability
Intel® eASIC™ devices offer custom low power1 2 3 4 5 6 solutions for a broad range of end markets such as 5G wireless, networking, military, cloud and storage, machine learning inference, consumer, video and broadcast and automotive applications.
Features
Power Advantage
Up to 80% lower power consumption than equivalent SRAM FPGAs.
Time Advantage
Faster time to market and turnaround time than traditional ASICs, with no PCB change from base FPGA design.
High Performance
Meeting the most demanding performance applications whether they are logic, DSP, data plane, or control plane applications.
Low Manufacturing Cost
One unique mask required for customization to lower development and manufacturing cost versus traditional ASICs.
Low Unit Cost
Using only the silicon area needed for the design, not more.
Fast Turnaround
Fast turnaround times allow for multiple chip revision at a fraction of the cost and time of a traditional ASIC.
Documentation
To access documentation for Intel® eASIC™ devices, you need a login.
產品與效能資訊
效能因使用情形、配置和其他因素而異。請造訪 www.Intel.com.tw/PerformanceIndex 進一步瞭解。
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