Intel Agilex® 7 FPGA and SoC FPGA I-Series
I 系列裝置為頻寬密集用途提供效能最高的 I/O 介面。Manufactured on Intel 10 nm SuperFin process technology, this series builds upon F-Series device features offering transceiver rates up to 116 Gbps, PCIe 5.0 support, and cache- and memory-coherent attach to processors with Compute Express Link (CXL)1.
Intel Agilex® 7 FPGA and SoC FPGA I-Series
Interconnect Innovations
116 Gbps
highest transceiver data rate1
The industry’s
1st
PCIe 5.0 x16 PCI-SIG listed, 32 GT/s FPGA2
4X
higher CXL bandwidth per port vs. other FPGA Compute Express Link (CXL) implementations3
116 Gbps
highest transceiver data rate1
The industry’s
1st
PCIe 5.0 x16 PCI-SIG listed, 32 GT/s FPGA2
4X
higher CXL bandwidth per port vs. other FPGA Compute Express Link (CXL) implementations3
Accelerate Workloads with Seamless Integration and High Bandwidth Processor Interfaces
In addition to fast and flexible programmable logic, Intel Agilex® 7 FPGAs feature high-bandwidth interfaces suitable for multiple applications across different markets.
Industry-Leading FPGA with R-Tile Chiplet
Learn more about how the R-Tile chiplet accelerates targeted data center and high-performance computing (HPC) workloads, empowering you to crunch numbers, analyze trends, and make record-time decisions with PCIe 5.0 and CXL 1.1 with some 2.0 features.
優勢
Support the Most Demanding Bandwidth Requirements
Support industry-leading data rates up to 116 Gbps for a wide range of applications while supporting demanding bandwidth requirements with configurable networking support, including hard media access control (MAC), physical coding sublayer (PCS), and forward error correction (FEC) for Ethernet rates up to 400GE.
High-performance and Scalable with Fast Data Transfer Rates
Optimize I/O functionality allowing multiple hosts to connect through PCI Express (PCIe) 5.0 x16 Interface for high-performance and scalability, with data transfer rates from 2.5 giga transfers per second (GT/s) to 32.0 GT/s.
High-Speed, Low-Latency Cache and Memory-Coherent Interface
The new Compute Express Link (CXL) protocol provides a high-speed, low-latency cache, and memory-coherent interface to CPUs and workload accelerators for optimal workload acceleration and connection to FPGA-based discrete accelerators.
使用案例與應用
I 系列滿足 400G IPU 與網路解決方案需求
Learn how I-Series devices deliver peak capacity, power efficiency, and performance for cloud (CSPs) and communications service providers (CoSPs) to improve revenue from infrastructure investment, lower total cost of ownership (TCO), increase networking capacity, security, and compute efficiency.
Intel Agilex® 7 FPGAs Target IPUs, SmartNICs, and 5G Networks
由於高速網路的攻擊暴增,從邊緣到雲端的網路攻擊與資料入侵安全挑戰日益艱鉅。With the growing threats of cyberattacks and data breaches, use cases for secure, encrypted communications are plentiful, ranging from Open vSwitch (OvS), 5G network, and network storage.
主要功能特色
Logic Elements (LEs)
Innovations allow over 4 million LEs in a single monolithic fabric.
Heterogeneous 3D SiP Transceivers
Transceivers on heterogeneous 3D system-in-package (SiP) tiles support bandwidth capacities ranging up to 32 Gbps NRZ, and up to 116 Gbps PAM4.
High-Performance Crypto Blocks
支援 AES-GCM 加密/解密、MACsec IP 的強化型 200G(半雙工)加密核心,可保護網路流量。
Quad-core Arm Cortex-A53 SoC
Integrated hardened quad-core Arm Cortex-A53 processor option.
其他資源
進一步探索 Intel® FPGA 裝置的相關內容,例如開發板、智慧財產、支援,還有更多。
產品與效能資訊
效能因使用情形、配置和其他因素而異。請造訪 www.Intel.com/PerformanceIndex 進一步瞭解。結果可能會有所落差。Intel 並不控制或審核第三方的資料。您應該參考其他來源以評估準確性。
根據 PCI-SIG 列出的 FPGA,Intel Agilex® FPGA R-Tile PCIe IP(5.0 x16,速度為 32 GT/s)。
Intel 估計時的依據為 Agilex FPGA CXL 硬體 IP + 軟體 IP 的測試結果(連結速度 5.0 x16 的 CXL)相較於使用第 3 方 CXL 軟體 IP(連結速度 4.0 x8 的 CXL)的 Xilinx FPGA,兩者皆以量產前的第 4 代 Intel® Xeon® 處理器進行過互通性測試。