Intel® Stratix® 10 FPGAs & SoC FPGA
Intel® Stratix® 10 FPGAs and SoCs deliver innovative advantages in performance, power efficiency, density, and system integration. Featuring the revolutionary Intel® Hyperflex™ FPGA Architecture and built combining Intel's patented Embedded Multi-Die Interconnect Bridge (EMIB) technology, the Advanced Interface Bus (AIB), and a growing portfolio of chiplets, Intel® Stratix® 10 devices deliver up to 2X performance gains over previous-generation, high-performance FPGAs.1
See also: Intel® Stratix® 10 FPGAs Design Software, Design Store, Downloads, Documentation, Community, and Support
Intel® Stratix® 10 FPGAs & SoC FPGA
Intel® Stratix® 10 GX FPGAs
Designed to meet the high-performance demands of high-throughput systems.
Intel® Stratix® 10 SX SoC FPGAs
Features hard processor system with 64 bit quad-core ARM* Cortex-A53 processor.
Intel® Stratix® 10 TX FPGAs
Delivers the most advanced transceiver capabilities in the industry by combining H- and E- transceiver tiles.
Intel® Stratix® 10 MX FPGAs
Essential multi-function accelerator for high performance computing (HPC).
Intel® Stratix® 10 DX FPGAs
Supports Intel® Ultra Path Interconnect for direct coherent connection to future select Intel® Xeon® Scalable processors.
Intel® Stratix® 10 NX FPGA
Designed to meet the high-performance demands of high-throughput systems.
Stratix® 10 FPGA Benefits and Features
Intel® Stratix® 10 FPGA devices address the design challenges in next-generation, high-performance systems in wireline and wireless communications, computing, storage, military, broadcast, medical, and test and measurement end markets.
Up to 2x Core Performance1
The ground breaking Intel® Hyperflex™ FPGA Architecture delivers up to 2X the core performance.1 With the Intel® Stratix® 10 Families you can extract high levels of performance with up to 8.6 TFLOPS of single-precision floating-point DSP performance and up to twenty 100 GbE interfaces.
Up to 7x Transceiver Bandwidth vs. Previous Generation FPGAs1
Breakthrough Bandwidth Barrier with up to 144 transceivers in a single device, with data rates up to 57.8 Gbps PAM-4 and 28.9 Gbps NRZ. Up to 287.5 Gbps of DDR4 memory bandwidth.Up to 512 Gbps of HBM2 memory bandwidth. PCIExpress hard and soft IP support up to Gen4 x16 at 16 GT/s per lane. Intel® Ultra Path Interconnect (Intel® UPI) hard IP with up to 20 lanes at 11.2 GT/s for direct cache coherent connection to future select Intel® Xeon® Scalable processors.
Up to 16 GB of HBM2 Memory in Package
Achieve Higher System Integration with the largest monolithic FPGA device with 2.8 million LEs and heterogeneous 3D SiP solutions including transceivers and other advanced components such as HBM2. Other system support includes standard external memories and Intel® Optane™ memory products. Intel® Stratix® 10 SoCs come packed with a 64 bit quad-core ARM* Cortex-A53 up to 1.35 GHz with hardened peripherals and high bandwidth interfaces directly to FPGA fabric at 30 Gbps.
Up to 143 INT8 TOPS or 286 INT4 TOPS2 for High Throughput AI Applications
The Intel® Stratix® 10 NX FPGA embed a new type of AI-optimized block called the AI Tensor Block. The AI Tensor Block is tuned for the common matrix-matrix or vector-matrix multiplications used in AI computations, with capabilities designed to work efficiently for both small and large matrix sizes. A single AI Tensor Block achieves 143 INT8 TOPS or 286 INT4 TOPS.2
Intel® Hyperflex™ FPGA Architecture
To address the challenges presented by next-generation systems, Intel® Stratix® 10 FPGAs and SoCs feature the new Intel® Hyperflex™ FPGA Architecture, which delivers 2X the clock frequency performance and up to 70% lower power compared to previous-generation, high-end FPGAs.1
Heterogeneous 3D Integration
Intel® Stratix® 10 FPGAs and SoCs leverage heterogeneous 3D System-in-Package (SiP) technology to integrate a monolithic FPGA core fabric with 3D SiP transceiver tiles and other advanced components in a single package.
Transceivers
Intel® Stratix® 10 FPGAs and SoCs deliver a new era of transceiver technology with the introduction of innovative heterogeneous 3D System-in-Package (SiP) transceivers.
External Memory Interfaces
Intel® Stratix® 10 devices provide memory interface support, including serial, parallel interfaces, and selected Intel® Optane™ DC persistent memory.
AI Tensor Blocks
The Intel® Stratix® 10 NX FPGA embed a new type of AI-optimized block called the AI Tensor Block. The AI Tensor Block is tuned for the common matrix-matrix or vector-matrix multiplications used in AI computations, with capabilities designed to work efficiently for both small and large matrix sizes. A single AI Tensor Block achieves up to 15X more INT82 throughput than standard Intel® Stratix® 10 FPGA DSP Block.
DSP
With Intel® Stratix® 10 devices, digital signal processing (DSP) designs can achieve up to 8.6 Tera floating point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations.
Interconnect to CPUs, ASICs, and ASSPs
Intel® Stratix® 10 DX devices accelerate applications used in Data Center, Networking, Cloud Computing, and Test & Measurement markets through hard and soft intellectual property blocks supporting both UPI and PCIe* Gen4 interfaces.
Hard Processor System
Building on Intel's leadership in SoCs, Intel® Stratix® 10 SoCs include a next-generation hard processor system (HPS) to deliver the industry's highest performance and most power-efficient SoCs.
Stratix® 10 SX SoC FPGA Benefits
Achieve High Levels of System Integration
Intel® Stratix® 10 SoCs empowers the USR in the ARM* ecosystem. ARM's next-generation 64-bit architecture (ARMv8) enabling enable hardware virtualization, system management and monitoring capabilities, and acceleration pre-processing. The ARM* Cortex-A53* processor supports 32-bit execution mode and board support packages for popular operating system including Linux*, Wind River’s VxWorks*, Micrium’s uC/OS-II* and uC/OS-III*, and more.
Achieve High Designer Productivity with Optimized FPGA and SoC Design Software
New engine optimized for multi-million logic elements (LE) FPGA designs providing significant reduction in design iterations, Intel® Stratix® 10 SoC Virtual Platform to enable early software development and verification, and C-based design entry using the Intel® FPGA SDK for OpenCL™, offering a design environment that is easy to implement on SoC FPGAs. Heterogeneous debug, profiling, and whole chip visualization with Intel® FPGA SoC FPGA Embedded Development Suite (EDS) featuring the ARM* Development Studio 5* (DS-5*) Intel® SoC FPGA Edition Toolkit.
Feature |
Description |
|---|---|
Processor |
Quad-core ARM* Cortex*–A53 MPCore* processor cluster up to 1.5 GHz |
Coprocessors |
Vector floating-point unit (VFPU) single and double precision, ARM* Neon* media processing engine for each processor |
Level 1 Cache |
32 KB L1 instruction cache with parity, 32 KB L1 data cache with error correction code (ECC) |
Level 2 Cache |
1 MB KB shared L2 cache with ECC |
On-Chip Memory |
256 KB on-chip RAM |
System Memory Management Unit |
System Memory Management Unit enables a unified memory model and extends hardware virtualization into peripherals implemented in the FPGA fabric |
Cache Coherency Unit |
Provides one-way (I/O) coherency that allows a CCU master to view the coherent memory of the ARM* Cortex*–A53 MPCore* CPUs |
Direct Memory Access (DMA) Controller |
8-channel direct memory access (DMA) |
Ethernet Media Access Controller (EMAC) |
3X 10/100/1000 EMAC with integrated DMA |
USB On-The-Go Controller (OTG) |
2X USB OTG with integrated DMA |
UART Controller |
2X UART 16550 compatible |
Serial Peripheral Interface (SPI) Controller |
4X SPI |
I2C Controller |
5X I2C |
SD/SDIO/MMC Controller |
1X eMMC 4.5 with DMA and CE-ATA support |
NAND Flash Controller |
1X ONFI 1.0 or later 8 and 16-bit support |
General-Purpose I/O (GPIO) |
Maximum 48 software-programmable GPIO |
| Timers | 4X general-purpose timers, 4X watchdog timers |
| System Manager | Contains memory-mapped control and status registers and logic to control system-level functions and other HPS modules |
| Reset Manager | Resets signals based on reset requests from sources in the HPS and FPGA fabric, and software writing to the module reset control registers |
| Clock Manager | Provides software-programmable clock control to configure all clocks generated in the HPS |
ASIC Prototyping
Higher productivity by reducing design partitioning complexity using monolithic FPGA fabric.
Cyber Security
fMAX over 900 MHz allows monitoring of all supported protocols at line rates.
Data Center Acceleration
UPI for direct coherent connection to future select Intel® Xeon® Scalable processor and PCIe Gen4 x16 along with Intel® Hyperflex™ FPGA Architecture, configurable DSP engines, and AI Tensor Blocks to enable breakthrough in computational throughput.
Wireline
fMAX over 700 MHz using the Intel® Hyperflex™ FPGA Architecture enabling 400G Ethernet.
Radar
Up to 8.6 TFLOPS of IEEE 754 compliant single-precision floating-point performance delivers GPU class performance at a fraction of the power.
OTN/Data Center Interconnect
Heterogeneous 3D System-in-Package (SiP) integration of transceiver tiles delivers 30G backplane support with a path to 57.8 Gbps and 28.9 Gbps.
Intel® Stratix® 10 Device Demo Videos
Introduction to Intel® Stratix® 10 DX FPGAs
Introducing Intel® Stratix® 10 DX FPGA for your high bandwidth and evolving data center requirements. It is the first FPGA to support Intel® Ultra Path Interconnect (Intel® UPI), PCIe* Gen4 x16 and select Intel® Optane™ DC persistent memory DIMMs.
Intel® Stratix® 10 DX Features Demo: Intel® Ultra Path Interconnect (Intel® UPI), PCIe* Gen4 x16, Intel® Optane™ DC Persistent Memory
Join Intel Engineers in the lab to learn more about the three main new features in the Intel® Stratix® 10 DX FPGAs: Intel® Ultra Path Interconnect (Intel® UPI), PCIe Gen4 x16 and Intel® Optane™ DC persistent memory DIMMs.
58G PAM-4 Transceivers
Applications needing massive I/O throughput such as Muxponder and Transponder systems, Optical Switches, and 5G networks need the performance of 58G PAM-4 transceiver I/O's, offered in Intel® Stratix® 10 TX FPGAs.
PCIe* Gen3 DMA to DDR4 SDRA
Intel® Stratix® 10 devices, which include PCIe* and memory controller hard IP blocks, when combined with Avalon® Memory Mapped and direct memory access functions, create a high-performance reference design.
28G Transceivers
In this video, we look at the unique transceiver architecture of Intel® Stratix® 10 FPGAs. See H-Tile transceivers that are connected via Intel's EMIB technology and operating at 28 Gbps backplane performance.
Intel® Hyperflex™ FPGA Architecture
Intel® Hyperflex™ FPGA Architecture in Intel® Stratix® 10 devices provides 2X the fMAX performance. This video shows a side-by-side comparison of an original design and a Hyper-Optimized design.
PCIe* Gen3 DMA to DDR4 SDRAM
Intel® Stratix® 10 devices, which include PCI Express* (PCIe*) and memory controller hard intellectual property (IP) blocks, combined with Avalon® memory-mapped interface and direct memory access (DMA) functions to create a high-performance reference design.
Samples and Ordering
Learn more about how to buy Intel® Programmable solutions, explore available development kits, and more.
Development Kits
Get information about hardware solutions and tools offered by Intel to accelerate the design process.
Powering FPGAs
See recommended Intel® Enpirion® Power Solutions and resources for powering Intel® FPGAs.
Ordering Codes
Decipher Intel® FPGA part numbers, including the significance of certain prefixes and package codes.
Where to Buy
Contact an Intel® Authorized Distributor today.
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產品與效能資訊
Comparison based on Stratix® V vs. Intel® Stratix® 10 using Intel® Quartus® Prime Pro 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Intel® Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Intel® Quartus® Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to Intel® Hyperflex™ FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users will achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com.tw/benchmarks.
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