White paper: Itanium® processors enhance parallelism on all levels for superior performance.
Intel Develops Explicitly Parallel Instruction Computing (EPIC)
The white paper focuses on the Explicitly Parallel Instruction Computing (EPIC) feature in the Intel® Itanium® processor 9500 series. EPIC principles exploit parallelism on all levels—pipeline, core, thread, memory, and instructions—delivering superior performance while benefiting from the mainframe-class reliability, availability, and serviceability features.
EPIC represents a paradigm shift in the development of instruction set architectures. Instead of placing the main burden of extracting parallelism and performance on the underlying computing hardware, a synergy is developed between the software ecosystem and the hardware implementation. This allows compilers, which have full access to the program source code, and the processors, which have full access to run-time information as a program executes, to be optimized for what each does best. In order to do this, the instruction set provides a rich set of features for software to optimally control the low-level hardware resources. This most notably includes the ability for compilers to specify, schedule, and exploit the many forms of parallelism inherent in user programs.