關鍵元件

產品集合
MAX® V CPLD
狀態
Launched
推出日期
2010
光刻
180 nm

相關資源

邏輯元素 (LE)
1270
Equivalent Macrocells
980
Pin-to-pin Delay
6.2 ns
User Flash Memory
8 Kb
Logic Convertible To Memory

功能

Internal Oscillator
Fast Power-on Reset
Boundary-scan JTAG
JTAG ISP
Fast Input Registers
Programmable Register Power-up
JTAG Translator
Real-time ISP
MultiVolt I/Os†
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5.0 V
I/O Power Banks
4
Maximum Output Enables
271
LVTTL/LVCMOS
Emulated LVDS Outputs
32 bit, 66 MHz PCI Compliant
1
Schmitt Triggers
Programmable Slew Rate
Programmable Pull-up Resistors
Programmable GND Pins
Open-drain Outputs
Bus Hold

封裝規格

封裝選項
F256, F324, T144
封裝大小
17mm x 17mm, 19mm x 19mm, 22mm x 22mm

補充資訊

額外資訊 URL