Arria 10 FPGA Development Kit User Guide
Arria 10 FPGA Development Kit Overview
General Description
Recommended Operating Conditions
- Recommended ambient operating temperature range: 0C to 45C
- Maximum ICC load current: 80A
- Maximum ICC load transient percentage: 35%
- FPGA maximum power supported by the supplied heatsink/fan: 100W
Handling the Board
Getting Started
Installing the Subscription Edition Software
Included in the Quartus Prime Standard Edition software are the Quartus Prime software, the Nios II® EDS, and the MegaCore IP Library. To install the Altera development tools, download the Quartus Prime Standard Edition software from the Quartus Prime Standard Edition software page of the Altera website.
Activating Your License
Purchasing this kit entitles you to a one-year license for the Development Kit Edition (DKE) of the Quartus Prime software. After the year, your DKE license will no longer be valid and you will not be permitted to use this version of the Quartus Prime software. To continue using the Quartus Prime software, you should download the free Quartus Prime Lite Edition or purchase a subscription to Quartus Prime Standard or Pro software.
Before using the Quartus Prime software, you must activate your license, identify specific users and computers, and obtain and install a license file. If you already have a licensed version of the subscription edition, you can use that license file with this kit. If not, follow these steps:
- Log on at the myAltera Account Sign In web page, and click Sign In.
- On the myAltera Home web page, click the Self-Service Licensing Center link.
- Locate the serial number printed on the side of the development kit box below the bottom bar code. The number consists of alphanumeric characters and does not contain hyphens.
- On the Self-Service Licensing Center web page, click the Find it with your License Activation Code link.
- In the Find/Activate Products dialog box, enter your development kit serial number and click Search.
- When your product appears, turn on the check box next to the product name.
- Click Activate Selected Products, and click Close.
- When licensing is complete, Altera emails a license.dat file to you. Store the file on your computer and use the License Setup page of the Options dialog box in the Quartus Prime software to enable the software.
Development Kit Package
Installing the USB-Blaster Driver
Installation instructions for the On-Board USB-Blaster II driver for your operating system are available on the Altera website. On the Altera Programming Cable Driver Information page of the Altera website, locate the table entry for your configuration and click the link to access the instructions.
Development Board Setup
Applying Power to the Board
If you suspect that your board might not be currently configured with the default settings, follow the instructions in the Default Switch and Jumper Settings section of this chapter.
Default Switch and Jumper Settings
Default Switch and Resistor Settings
Factory Reset
To do a factory reset, follow these steps:
-
Select "Restore -> Factory Restore".
Figure 9. Arria 10 FPGA Board Test System Factory Restore Select
-
Set the correct board information and then click restore. The
restore process takes about 10 minutes.
Figure 10. Factory Restore Window
Board Test System
The Board Test System (BTS) provides an easy-to-use interface to alter functional settings and observe the results. You can use the BTS to test board components, modify functional parameters, observe performance, and measure power usage.
While using the BTS, you reconfigure the FPGA several times with test designs specific to the functionality you are testing. Several designs are provided to test the major board features. Each design provides data for one or more tabs in the application. The Configure menu identifies the appropriate design to download to the FPGA for each tab.
After successful FPGA configuration, the appropriate tab appears that allows you to exercise the related board features. Highlights appear in the board picture around the corresponding components.
The BTS communicates over the JTAG bus to a test design running in the FPGA. The Board Test System and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the SignalTap® II Embedded Logic Analyzer. Because the BTS is designed based on the Quartus Programmer and System Console, be sure to close other applications before you use the BTS application.
Preparing the Board
Running the Board Test System
To run the Board Test System (BTS), navigate to the <package dir>\examples\board_test_system directory and run the BoardTestSystem.exe application.
A GUI appears, displaying the application tab that corresponds to the design running in the FPGA. The development board’s flash memory ships preconfigured with the design that corresponds to the GPIO tab.
The BTS will pick up the Quartus Programmer to configure the FPGA device on your development kit. Make sure the Quartus Prime software you are using is the version supporting the FPGA silicon on the board.
Version Selector
The BTS will prompt you with a Version Selector window once opened. You can also open the Version Selector window through the Configure tab by clicking Select Silicon Version. Select the silicon version of the Arria 10 device that is installed on your board.
If you do not know, or are unsure of the version, enter the board serial number in the box on the right and the software will pick the right version based on the table below. The numbers here are the last 3-4 digits of the serial number which can be found on the bottom of your board.
| Serial Number | Arria 10 Silicon Revision |
|---|---|
| 10APCIe000[< 0332] | ES2 |
| 10APCIe000[0332 – 0383] | PRD-1 |
| 10APCIe000[0500 – 0999] | ES3 |
| 10APCIe000[1000+] | PRD |
Using the Board Test System
Using the Configure Menu
To configure the FPGA with a test system design, perform the following steps:
- On the Configure menu, click the configure command that corresponds to the functionality you wish to test.
- In the dialog box that appears, click Configure to download the corresponding design to the FPGA.
- When configuration finishes, close the Quartus Programmer if open. The design begins running in the FPGA. The corresponding GUI application tabs that interface with the design are now enabled.
The System Info Tab
| Controls | Description |
|---|---|
| Board Information Controls | The board information is updated once the GPIO design is configured. Otherwise, this control displays the default static information about your board. |
| Board Name | Indicates the official name of the board, given by the Board Test System. |
| Board P/N | Indicates the part number of the board. |
| Serial Number | Indicates the serial number of the board. |
| Factory Test Version | Indicates the version of the Board Test System currently running on the board. |
| MAC | Indicates the MAC address of the board. |
| MAX V Control |
Allows you to view and change the current register values, which take effect immediately: System Reset (SRST) — Write only. Click to reset the FPGA. Page Select Override (PSO) — Read/Write Page Select Register (PSR) — Read/Write Page Select Switch (PSS) — Read only MAX Ver: Indicates the version of MAX V code currently running on the board. |
| JTAG Chain | Shows all the devices currently in the JTAG chain. |
| Qsys Memory Map | Shows the memory map of the Qsys system on your board. |
The GPIO Tab
| Character LCD | Allows you to display text strings on the character LCD on your board. Type text in the text boxes and then click Display. |
| User DIP Switch | Displays the current positions of the switches in the user DIP switch bank (SW2). Change the switches on the board to see the graphical display change accordingly. |
| User LEDs | Displays the current state of the user LEDs for the FPGA. To toggle the board LEDs, click the 0 to 7 buttons to toggle red or green LEDs, or click the All button. |
| Push Button Switches | Read-only control displays the current state of the board user push buttons. Press a push button on the board to see the graphical display change accordingly. |
The Flash Tab
| Control | Description |
|---|---|
| Read | Reads the flash memory on your board. To see the flash memory contents, type a starting address in the text box and click Read. Values starting at the specified address appear in the table. |
| Write | Writes the flash memory on your board. To update the flash memory contents, change values in the table and click Write. The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents. |
| Random Test | Starts a random data pattern test to flash memory, limited to the 512 K test system scratch page. |
| CFI Query | Updates the memory table, displaying the CFI ROM table contents from the flash device. |
| Increment Test | Starts an incrementing data pattern test to flash memory, limited to the 512 K test system scratch page. |
| Reset | Executes the flash device’s reset command and updates the memory table displayed on the Flash tab. |
| Erase | Erases flash memory. |
| Flash Memory Map | Displays the flash memory map for the development board. |
The XCVR Tab
| Control | Description |
|---|---|
| Status | Displays the following status
information during a loopback test:
PLL lock—Shows the PLL locked or unlocked state. Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected. Details—Shows the PLL lock and pattern sync status: 
|
| Port | Allows you to specify which
interface to test. The following port tests are available:
QSFP x4 SFP x1 SMA x1 SDI x1 |
| PMA Setting | Allows you to make changes to the
PMA parameters that affect the active transceiver interface. The
following settings are available for analysis:
Serial Loopback—Routes signals between the transmitter and the receiver. VOD—Specifies the voltage output differential of the transmitter buffer. Pre-emphasis tap
Equalizer—Specifies the AC gain setting for the receiver equalizer in four stage mode. DC gain—Specifies the DC gain setting for the receiver equalizer in four stage mode. VGA—Specifies the VGA gain value. All PMA settings should be changed as in Figure 2. |
| Data Type | Specifies the type of data
contained in the transactions. The following data types are
available for analysis:
|
| Error Control | Displays data errors detected
during analysis and allows you to insert errors:
|
| Loopback |
Start—Initiates the selected ports transaction performance analysis. Note: Always click Clear before Start.
Stop—Terminates transaction performance analysis. TX and RX performance bars—Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve. |
The PCIe Tab
| Control | Description |
|---|---|
| Status | Displays the following status information during a
loopback test:
PLL lock—Shows the PLL locked or unlocked state. Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected. Details—Shows the PLL lock and pattern sync status:
|
| Port | PCIe x8 Gen3 |
| PMA Setting | Allows you to make changes to the PMA parameters that
affect the active transceiver interface. The following settings are
available for analysis:
Serial Loopback—Routes signals between the transmitter and the receiver. VOD—Specifies the voltage output differential of the transmitter buffer. Pre-emphasis
tap
Equalizer—Specifies the AC gain setting for the receiver equalizer in four stage mode. DC gain—Specifies the DC gain setting for the receiver equalizer in four stage mode. VGA—Specifies the VGA gain value. All PMA settings should be changed as in Figure 2. |
| Data Type | Specifies the type of data
contained in the transactions. The following data types are
available for analysis:
|
| Error Control | Displays data errors detected
during analysis and allows you to insert errors:
|
| Loopback |
Start—Initiates the selected ports transaction performance analysis. Note: Always click Clear before Start.
Stop—Terminates transaction performance analysis. TX and RX performance bars—Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve. |
The FMC A Tab
| Control | Description |
|---|---|
| Status | Displays the following status information during a
loopback test:
PLL lock—Shows the PLL locked or unlocked state. Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected. Details—Shows the PLL lock and pattern sync status:
|
| Port | Allows you to specify which interface to test. The
following port tests are available:
XCVR CMOS |
| PMA Setting | Allows you to make changes to the PMA parameters that
affect the active transceiver interface. The following settings are
available for analysis:
Serial Loopback—Routes signals between the transmitter and the receiver. VOD—Specifies the voltage output differential of the transmitter buffer. Pre-emphasis
tap
Equalizer—Specifies the AC gain setting for the receiver equalizer in four stage mode. DC gain—Specifies the DC gain setting for the receiver equalizer in four stage mode. VGA—Specifies the VGA gain value. All PMA settings should be changed as in Figure 2. |
| Data Type | Specifies the type of data
contained in the transactions. The following data types are
available for analysis:
|
| Error Control | Displays data errors detected
during analysis and allows you to insert errors:
|
| Loopback |
Start—Initiates the selected ports transaction performance analysis. Note: Always click Clear before Start.
Stop—Terminates transaction performance analysis. TX and RX performance bars—Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve. |
The FMC B Tab
| Control | Description |
|---|---|
| Status | Displays the following status information during a
loopback test:
PLL lock—Shows the PLL locked or unlocked state. Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected. Details—Shows the PLL lock and pattern sync status:
|
| Port | Allows you to specify which interface to test. The
following port tests are available:
XCVR CMOS |
| PMA Setting | Allows you to make changes to the PMA parameters that
affect the active transceiver interface. The following settings are
available for analysis:
Serial Loopback—Routes signals between the transmitter and the receiver. VOD—Specifies the voltage output differential of the transmitter buffer. Pre-emphasis
tap
Equalizer—Specifies the AC gain setting for the receiver equalizer in four stage mode. DC gain—Specifies the DC gain setting for the receiver equalizer in four stage mode. VGA—Specifies the VGA gain value. All PMA settings should be changed as in Figure 2. |
| Data Type | Specifies the type of data
contained in the transactions. The following data types are
available for analysis:
|
| Error Control | Displays data errors detected
during analysis and allows you to insert errors:
|
| Loopback |
Start—Initiates the selected ports transaction performance analysis. Note: Always click Clear before Start.
Stop—Terminates transaction performance analysis. TX and RX performance bars—Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve. |
The DDR3 Tab
| Control | Description |
|---|---|
| Start | Initiates DDR3 memory transaction performance analysis. |
| Stop | Terminates transaction performance analysis. |
| Performance Indicators | These controls display current transaction performance
analysis information collected since you last clicked
Start:
|
| Error Control | This control displays data errors detected during
analysis and allows you to insert errors:
|
| Number of Addresses to Write and Read | Determines the number of addresses to use in each iteration of reads and writes. |
The DDR4 Tab
| Control | Description |
|---|---|
| Start | Initiates DDR4 memory transaction performance analysis. |
| Stop | Terminates transaction performance analysis. |
| Performance Indicators | These controls display current transaction performance
analysis information collected since you last clicked
Start:
|
| Error Control | This control displays data errors detected during
analysis and allows you to insert errors:
|
| Number of Addresses to Write and Read | Determines the number of addresses to use in each iteration of reads and writes. |
The Power Monitor
| Control | Description |
|---|---|
| Test Settings | Displays the following controls:
Power Rail—Indicates the currently-selected power rail. After selecting the desired rail, click Reset to refresh the screen with updated board readings. Scale—Specifies the amount to scale the power graph. Select a smaller number to zoom in to see finer detail. Select a larger number to zoom out to see the entire range of recorded values. Speed—Specifies how often to refresh the graph. |
| Power Information | Displays root-mean-square (RMS) current, maximum, and minimum numerical power readings in mA. |
| Graph | Displays the mA power consumption of your board over time. The green line indicates the current value. The red line indicates the maximum value read since the last reset. The yellow line indicates the minimum value read since the last reset. |
| General Information | Displays MAX V version and current temperature of the FPGA and board. |
| Reset | Clears the graph, resets the minimum and maximum values, and restarts the Power Monitor. |
The Clock Control
| Control | Description |
|---|---|
| Serial Port Registers | Shows the current values from the Si570 registers for frequency configuration. |
| Target frequency (MHZ) | Allows you to specify the frequency of the clock. Legal values are between 10 and 810 MHz with eight digits of precision to the right of the decimal point. For example, 421.31259873 is possible within 100 parts per million (ppm). The Target frequency control works in conjunction with the Set New Freq control. |
| fXTAL | Shows the calculated internal fixed-frequency crystal, based on the serial port register values. |
| Default | Sets the frequency for the oscillator associated with the active tab back to its default value. This can also be accomplished by power cycling the board. |
| Set New Freq | Sets the programmable oscillator frequency for the selected clock to the value in the Target frequency control for the programmable oscillators. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Altera recommends resetting the FPGA logic after changing frequencies. |
| Control | Description |
|---|---|
| F_vco | Displays the generating signal value of the voltage-controlled oscillator. |
| Registers | Display the current frequencies for each oscillator. |
| Frequency (MHz) | Allows you to specify the frequency of the clock. |
| Disable all | Disable all oscillators at once. |
| Read | Reads the current frequency setting for the oscillator associated with the active tab. |
| Default | Sets the frequency for the oscillator associated with the active tab back to its default value. This can also be accomplished by power cycling the board. |
| Set New Freq | Sets the programmable oscillator frequency for the selected clock to the value in the CLK0 to CLK3 controls for the Si5338 (U26 and U14). Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Altera recommends resetting the FPGA logic after changing frequencies. |
| Import Reg Map | Import register map file generated from Silicon Laboratories ClockBuilder Desktop. |
Board Update Portal
The Arria 10 GX FPGA Development Kit ships with the Board Update Portal design example stored in the factory portion of the flash memory. The design consists of a Nios II embedded processor, an Ethernet MAC, and an HTML web server.
When you power up the board with SW6.4 FACTORY_LOAD in the default position, the Arria 10 GX FPGA configures with the Board Update Portal design example. The design can obtain an IP address from any DHCP server and serve a web page from the flash on your board to any host computer on the same network. The web page allows you to upload new FPGA designs to the user portion of the flash memory and provides links to useful information on the Altera website, including kit-specific links and design resources.
After successfully updating the user flash memory, you can load the user design from the flash memory into the FPGA. To do so, set SW6.4 to OFF position and power cycle the board.
The source code for the Board Update Portal design resides in the <package dir>\examples\board_update_portal directory. If the Board Update Portal is corrupted or deleted from the flash memory, refer to the “Factory Reset” section for information on how to restore the boards original factory contents.
Connecting to the Board Update Portal Web Page
This section provides instructions to connect to the Board Update Portal web page. Before you proceed, ensure that you have the following:
- A PC with a connection to a working Ethernet port on a DHCP enabled network.
- A separate working Ethernet port connected to the same network for the board.
- The Ethernet cable, power cables, and development board that are included in the kit.
To connect to the Board Update Portal web page, perform these steps:
- Install the latest Altera software tools, including the Quartus Prime software, Nios II processor and IP functions. If necessary, download the Quartus Prime Lite Edition software.
- With the board powered down, set SW6.4 to the ON position.
- Attach the Ethernet cable from the board to your LAN.
- Power up the board. The board connects to the LAN's gateway router and obtains an IP address. The LCD on the board will display the IP address.
- Launch a web browser on the PC that is connected to the same network, and enter the IP address from the LCD into the browser address bar. The Board Update Portal web page will appear in the browser.
You can click Arria 10 GX FPGA Development Kit on the Board Update Portal web page to access the kit’s home page for documentation updates and additional new designs.
You can also navigate directly to the Arria 10 GX FPGA Development Kit page of the Altera website to determine if you have the latest kit software.
Using the Board Update Portal to Update User Designs
The Board Update Portal allows you to write new designs to the user portion of the flash memory. Designs must be in the Nios II Flash Programmer File (.flash) format.
Design files available from the Arria 10 GX FPGA Development Kit page include .flash files. You can also create .flash files from your own custom designs.
To upload a design over the network into the user portion of the flash memory on your board, perform the following steps:
- Perform the steps in “Connecting to the Board Update Portal Web Page” section to access the Board Update Portal web page.
- In the Hardware File Name field specify the .flash file that you either downloaded from the Altera website or created on your own. If there is a software component to the design, specify it in the same manner using the Software File Name field or otherwise leave the field blank.
- Click Upload. The progress bar indicates the percent complete. The file will take about 20 seconds to upload.
- To configure the FPGA with the new design after the flash memory upload process is complete, set SW6.4 to the OFF position.
As long as you don’t overwrite the factory image in the flash memory device, you can continue to use the Board Update Portal to write new designs to the user portion of the flash memory. If you do overwrite the factory image, you can restore it by following the instructions in the “Factory Reset” section.
Board Components
A complete set of schematics, a physical layout database, and GERBER files for the development board reside in the development kit documents directory.
Board Overview
| Board Reference | Type | Description |
|---|---|---|
| Featured Devices | ||
| U28 | FPGA | Arria 10 GX FPGA, 10AX115S2F45I1SG:
|
| U16 | CPLD | MAX V CPLD, 2210 LEs, 256FBGA 1.8V VCCINT |
| Board Reference | Type | Description |
| Configuration and Setup Elements | ||
| J3 | On-Board USB-Blaster II | Micro-USB 2.0 connector for programming and debugging the FPGA. |
| SW3 | PCI Express Control DIP switch | Enables PCI Express link widths x1, x4, and x8. |
| SW4 | JTAG Bypass DIP switch | Enables and disables devices in the JTAG chain. This switch is located on the back of the board. |
| SW5 | FPP Configuration DIP Switch | Sets the Arria 10 MSEL pins and VID_EN pin. |
| SW6 | Board settings DIP switch | Controls the MAX V CPLD System Controller functions such as clock select, clock enable, factory or user design load from flash and FACTORY signal command sent at power up. This switch is located at the bottom of the board. |
| S4 | CPU reset push button | The default reset for the FPGA logic. |
| S5 | Image select push button | Toggles the configuration LEDs which selects the program image that loads from flash memory to the FPGA. |
| S6 | Program configuration push button | Configures the FPGA from flash memory image based on the program LEDs. |
| S7 | MAX V reset push button | The default reset for the MAX V CPLD System Controller. |
| Board Reference | Type | Description |
| Status Elements | ||
| D22, D23 | JTAG LEDs | Indicates transmit or receive activity of the JTAG chain. The TX and RX LEDs flicker if the link is in use and active. |
| D24, D25 | System Console LEDs | Indicates the transmit or receive activity of the System Console USB interface. The TX and RX LEDs would flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle. |
| D12, D13, D14 | Program LEDs | Illuminates to show the LED sequence that determines which flash memory image loads to the FPGA when you press the program load push button. |
| D17 | Configuration done LED | Illuminates when the FPGA is configured. |
| D15 | Load LED | Illuminates during FPGA configuration. |
| D16 | Error LED | Illuminates when the FPGA configuration from flash fails. |
| D19 | Power LED | Illuminates when the board is powered on. |
| D32 | Temperature LED | Illuminates when an over temperature condition occurs for the FPGA device. Ensure that an adequate heatsink/fan is properly installed.. |
| D26, D27, D28, D29, D30 | Ethernet LEDs | Shows the connection speed as well as transmit or receive activity. |
| D33 | SDI Cable LED | Illuminates to show the transmit or receive activity. |
| D34, D35, D36, D37, D38 | PCI Express link LEDs | You can configure these LEDs to display the PCI Express link width (x1, x4, x8) and data rate. |
| D3, D4, D5, D6, D7, D8, D9, D10 | User defined LEDs | Eight bi-color LEDs (green and red) for 16 user LEDs. Illuminates when driven low. |
| D1, D2, D11 | FMCA LEDs | Illuminates for RX, TX, PRSNTn activity. |
| D18, D20, D21 | FMCB LEDs | Illuminates for RX, TX, PRSNTn activity. |
| Board Reference | Type | Description |
| Clock Circuitry | ||
| X1 | SDI reference clock | SW6.3 DIP switch controlled:
FS=0: 148.35 MHz FS=1: 148.50 MHz |
| X3 | Programmable oscillator | Si570 programmable oscillator by the clock control GUI. Default is 100 MHz. |
| X2 | 125.0-MHz oscillator | 125.0-MHz voltage controlled crystal oscillator for the Ethernet interface.. |
| X4 | 50-MHz oscillator | 50.000-MHz crystal oscillator for general purpose logic. |
| U26 | Quad-output oscillator | Si5338 programmable oscillator for clock control GUI. (Defaults CLK[0:3] = 270MHz, 644.53125MHz, 644.53125MHz, 133.33MHz) |
| U14 | Quad-output oscillator | Si5338 programmable oscillator for clock control GUI. (Defaults CLK[0:3] = 100MHz, 625MHz, 625MHz, 302.083333MHz) |
| J6 | Clock input SMA connector | Signal: CLKIN_SMA |
| J7 | Clock output SMA connector | Signal: SMA_CLK_OUT |
| J20, J21 | SDI (Serial Digital Interface) transceiver connectors | Two sub-miniature version B (SMB) connectors. Drives serial data input/output to or from SDI video port. |
| Board Reference | Type | Description |
| Transceiver Interfaces | ||
| J15 | SMA connector | SMA_TX_N from the left transceiver bank - 1H |
| J16 | SMA connector | SMA_TX_P from the left transceiver bank - 1H |
| Board Reference | Type | Description |
| General User Input/Output | ||
| SW2 | FPGA user DIP switch | Octal user DIP switches. When the switch is ON, a logic 0 is selected. |
| S1, S2, S3 | General user push buttons | Three user push buttons. Driven low when pressed. |
| D3, D4, D5, D6, D7, D8, D9, D10 | User defined LEDs | Eight bi-color user LEDs. Illuminates when driven low. |
| Board Reference | Type | Description |
| Memory Devices | ||
| J14 | HiLo Connector | One x72 memory interface
supporting DDR3 (x72), DDR4 (x72), QDR4 (x36), and RLDRAM 3 (x36).
This development kit includes three plugin
modules (daughtercards) that use the HiLo connector:
|
| U4, U5 | Flash memory | ICS - 1GBIT STRATA FLASH, 16-BIT DATA, VCC=VCCQ=1.7V-2.0V, 64-BALL EASY BGA (10MM X 8MM) |
| Board Reference | Type | Description |
| Communication Ports | ||
| J22 | PCI Express x8 edge connector | Made of gold-plated edge fingers for up to ×8 signaling in either Gen1, Gen2, or Gen3 mode. |
| J1, J2 | FMC Port | FPGA mezzanine card ports A and B. |
| J9 | Gbps Ethernet RJ-45 connector | RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed Ethernet MAC MegaCore function in SGMII mode. |
| J18 | QSFP interface | Provides four transceiver channels for a 40G QSFP module. |
| J12 | SFP+ connector | SFP+ XCVR interface. |
| J3 | Micro-USB connector | Embedded Altera USB-Blaster II JTAG for programming the FPGA via a USB cable. |
| Board Reference | Type | Description |
| Display Ports | ||
| J5 | DisplayPort connector | Molex 0.50mm pitch DisplayPort male receptacle, right angle, surface mount, 0.76µm gold plating, 20 circuits with cover. |
| B2 | Character LCD | Connector which interfaces to the provided 16 character × 2 line LCD module. |
| J20, J21 | SDI video port | Two sub-miniature version B (SMB) connectors that provide a full-duplex SDI interface. |
| Board Reference | Type | Description |
| Power Supply | ||
| J22 | PCI Express edge connector | Interfaces to a PCI Express root port such as an appropriate PC motherboard. |
| J13 | DC input jack | Accepts a 12-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express slot. |
| SW1 | Power Switch | Switch to power on or off the board when power is supplied from the DC input jack. |
| J4 | PCIe 2x4 ATX power connector | 12-V ATX input. This input must be connected when the board is plugged into a PCIe root port. |
MAX V CPLD System Controller
The board utilizes the EPM2210 System Controller, an Altera MAX V CPLD, for the following purposes:
- FPGA configuration from flash memory
- Power consumption monitoring
- Temperature monitoring
- Fan control
- Control registers for clocks
- Control registers for remote update system
|
Schematic Signal Name |
Pin Number |
I/O Standard | Description |
|---|---|---|---|
|
CLK125_EN |
E9 |
2.5 V |
125 MHz oscillator enable |
|
CLK50_EN |
J16 |
1.8 V |
50 MHz oscillator enable |
|
CLK_CONFIG |
J5 |
1.8 V |
Clock Configure |
|
CLK_ENABLE |
D4 |
2.5 V |
Clock Enable |
|
CLK_SEL |
A2 |
2.5 V |
Clock Select |
|
CLOCK_I2C_SCL |
C12 |
2.5 V |
Serial clock line for I2C |
|
CLOCK_I2C_SDA |
C10 |
2.5 V |
Serial data line for I2C |
|
CPU_RESETN |
K4 |
1.8 V |
FPGA reset push button |
|
FACTORY_LOAD |
B5 |
2.5 V |
DIP switch to load factory or user design at power-up |
|
FLASH_ADVN |
N14 |
1.8 V |
FSM bus flash memory address valid |
|
FLASH_CEN0 |
D14 |
1.8 V |
FSM bus flash memory chip enable |
|
FLASH_CEN1 |
F11 |
1.8 V |
FSM bus flash memory chip enable |
|
FLASH_CLK |
N15 |
1.8 V |
FSM bus flash memory clock |
|
FLASH_OEN |
P14 |
1.8 V |
FSM bus flash memory output enable |
|
FLASH_RDYBSYN0 |
F12 |
1.8 V |
FSM bus flash memory ready |
|
FLASH_RDYBSYN1 |
P15 |
1.8 V |
FSM bus flash memory ready |
|
FLASH_RESETN |
D13 |
1.8 V |
FSM bus flash memory reset |
|
FLASH_WEN |
J1 |
1.8 V |
FSM bus flash memory write enable |
|
FM_A1 |
F15 |
1.8 V |
FM address bus |
|
FM_A2 |
G16 |
1.8 V |
FM address bus |
|
FM_A3 |
G15 |
1.8 V |
FM address bus |
|
FM_A4 |
H16 |
1.8 V |
FM address bus |
|
FM_A5 |
H15 |
1.8 V |
FM address bus |
|
FM_A6 |
F16 |
1.8 V |
FM address bus |
|
FM_A7 |
G14 |
1.8 V |
FM address bus |
|
FM_A8 |
D16 |
1.8 V |
FM address bus |
|
FM_A9 |
E15 |
1.8 V |
FM address bus |
|
FM_A10 |
E16 |
1.8 V |
FM address bus |
|
FM_A11 |
H14 |
1.8 V |
FM address bus |
|
FM_A12 |
D15 |
1.8 V |
FM address bus |
|
FM_A13 |
F14 |
1.8 V |
FM address bus |
|
FM_A14 |
C14 |
1.8 V |
FM address bus |
|
FM_A15 |
C15 |
1.8 V |
FM address bus |
|
FM_A16 |
H3 |
1.8 V |
FM address bus |
|
FM_A17 |
H2 |
1.8 V |
FM address bus |
|
FM_A18 |
E13 |
1.8 V |
FM address bus |
|
FM_A19 |
F13 |
1.8 V |
FM address bus |
|
FM_A20 |
G13 |
1.8 V |
FM address bus |
|
FM_A21 |
G12 |
1.8 V |
FM address bus |
|
FM_A22 |
E12 |
1.8 V |
FM address bus |
|
FM_A23 |
J13 |
1.8 V |
FM address bus |
|
FM_A24 |
G5 |
1.8 V |
FM address bus |
|
FM_A25 |
H13 |
1.8 V |
FM address bus |
|
FM_A26 |
H4 |
1.8 V |
FM address bus |
|
FM_D0 |
J15 |
1.8 V |
FM data bus |
|
FM_D1 |
L16 |
1.8 V |
FM data bus |
|
FM_D2 |
L14 |
1.8 V |
FM data bus |
|
FM_D3 |
K14 |
1.8 V |
FM data bus |
|
FM_D4 |
L13 |
1.8 V |
FM data bus |
|
FM_D5 |
L15 |
1.8 V |
FM data bus |
|
FM_D6 |
M15 |
1.8 V |
FM data bus |
|
FM_D7 |
M16 |
1.8 V |
FM data bus |
|
FM_D8 |
K16 |
1.8 V |
FM data bus |
|
FM_D9 |
K15 |
1.8 V |
FM data bus |
|
FM_D10 |
J14 |
1.8 V |
FM data bus |
|
FM_D11 |
K13 |
1.8 V |
FM data bus |
|
FM_D12 |
L12 |
1.8 V |
FM data bus |
|
FM_D13 |
N16 |
1.8 V |
FM data bus |
|
FM_D14 |
M13 |
1.8 V |
FM data bus |
|
FM_D15 |
L11 |
1.8 V |
FM data bus |
|
FM_D16 |
E4 |
1.8 V |
FM data bus |
|
FM_D17 |
F6 |
1.8 V |
FM data bus |
|
FM_D18 |
F4 |
1.8 V |
FM data bus |
|
FM_D19 |
C2 |
1.8 V |
FM data bus |
|
FM_D20 |
D1 |
1.8 V |
FM data bus |
|
FM_D21 |
F1 |
1.8 V |
FM data bus |
|
FM_D22 |
E3 |
1.8 V |
FM data bus |
|
FM_D23 |
G2 |
1.8 V |
FM data bus |
|
FM_D24 |
E5 |
1.8 V |
FM data bus |
|
FM_D25 |
C3 |
1.8 V |
FM data bus |
|
FM_D26 |
D3 |
1.8 V |
FM data bus |
|
FM_D27 |
D2 |
1.8 V |
FM data bus |
|
FM_D28 |
E1 |
1.8 V |
FM data bus |
|
FM_D29 |
G3 |
1.8 V |
FM data bus |
|
FM_D30 |
F3 |
1.8 V |
FM data bus |
|
FM_D31 |
F2 |
1.8 V |
FM data bus |
|
FMCA_C2M_PG |
R16 |
1.8 V |
FMC port A power good output |
|
FMCA_PRSNTN |
G1 |
1.8 V |
Green LED. Illuminates when the FMC port has a board or cable plugged-in. Driven by the add-in card. |
|
FMCB_C2M_PG |
L5 |
1.8 V |
FMC port B power good output |
|
FMCB_PRSNTN |
E2 |
1.8 V |
Green LED. Illuminates when the FMC port has a board or cable plugged-in. Driven by the add-in card. |
|
FPGA_CONF_DONE |
K1 |
1.8 V |
FPGA configuration done LED |
|
FPGA_CONFIG_D0 |
R1 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D1 |
T2 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D2 |
N6 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D3 |
N5 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D4 |
N7 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D5 |
N8 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D6 |
M12 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D7 |
T13 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D8 |
T15 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D9 |
R13 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D10 |
P4 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D11 |
R3 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D12 |
T10 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D13 |
P5 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D14 |
R4 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D15 |
R5 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D16 |
M8 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D17 |
M7 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D18 |
T5 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D19 |
P9 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D20 |
M6 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D21 |
N9 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D22 |
R8 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D23 |
T8 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D24 |
P7 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D25 |
R7 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D26 |
R9 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D27 |
T9 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D28 |
T7 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D29 |
P8 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D30 |
R6 |
1.8 V |
FPGA configuration data |
|
FPGA_CONFIG_D31 |
P6 |
1.8 V |
FPGA configuration data |
|
FPGA_CVP_CONFDONE |
M14 |
1.8 V |
FPGA Configuration via Protocol (CvP) done |
|
FPGA_DCLK |
M9 |
1.8 V |
FPGA configuration clock |
|
FPGA_NCONFIG |
E14 |
1.8 V |
FPGA configuration active |
|
FPGA_NSTATUS |
J4 |
1.8 V |
FPGA configuration ready |
|
FPGA_PR_DONE |
H12 |
1.8 V |
FPGA partial reconfiguration done |
|
FPGA_PR_ERROR |
K12 |
1.8 V |
FPGA partial reconfiguration error |
|
FPGA_PR_READY |
P12 |
1.8 V |
FPGA partial reconfiguration ready |
|
FPGA_PR_REQUEST |
T4 |
1.8 V |
FPGA partial reconfiguration request |
|
M5_JTAG_TCK |
P3 |
1.8 V |
JTAG chain clock |
|
M5_JTAG_TDI |
L6 |
1.8 V |
JTAG chain data in |
|
M5_JTAG_TDO |
M5 |
1.8 V |
JTAG chain data out |
|
M5_JTAG_TMS |
N4 |
1.8 V |
JTAG chain mode |
|
MAX5_BEN0 |
R10 |
1.8 V |
MAX V Byte Enable 0 |
|
MAX5_BEN1 |
M10 |
1.8 V |
MAX V Byte Enable 1 |
|
MAX5_BEN2 |
T12 |
1.8 V |
MAX V Byte Enable 2 |
|
MAX5_BEN3 |
P10 |
1.8 V |
MAX V Byte Enable 3 |
|
MAX5_CLK |
N11 |
1.8 V |
MAX V Clock |
|
MAX5_CSN |
T11 |
1.8 V |
MAX V chip select |
|
MAX5_OEN |
N10 |
1.8 V |
MAX V output enable |
|
MAX5_WEN |
R11 |
1.8 V |
MAX V Write enable |
|
MAX_CONF_DONE |
D7 |
2.5 V |
On-board USB-Blaster II configuration done LED |
|
MAX_ERROR |
C7 |
2.5 V |
FPGA configuration error LED |
|
MAX_LOAD |
B6 |
2.5 V |
FPGA configuration active LED |
|
MAX_RESETN |
J3 |
1.8 V |
MAX V reset push button |
|
MSEL0 |
R12 |
1.8 V |
FPGA MSEL0 setting |
|
MSEL1 |
P11 |
1.8 V |
FPGA MSEL1 setting |
|
MSEL2 |
M11 |
1.8 V |
FPGA MSEL2 setting |
|
MV_CLK_50 |
J12 |
1.8 V |
MAX V 50 MHz clock |
|
OVERTEMP |
E11 |
2.5 V |
Temperature monitor fan enable |
|
OVERTEMPN |
B16 |
2.5 V |
Temperature monitor fan enable |
|
PGM_CONFIG |
A6 |
2.5 V |
Load the flash memory image identified by the PGM LEDs |
|
PGM_LED0 |
D6 |
2.5 V |
Flash memory PGM select indicator 0 |
|
PGM_LED1 |
C6 |
2.5 V |
Flash memory PGM select indicator 1 |
|
PGM_LED2 |
B7 |
2.5 V |
Flash memory PGM select indicator 2 |
|
PGM_SEL |
A7 |
2.5 V |
Toggles the PGM_LED[2:0] LED sequence |
|
SDI_MF0_BYPASS |
P13 |
1.8 V |
SDI Interface Mode Select 0 / Bypass control |
|
SDI_MF1_AUTO_SLEEP |
R14 |
1.8 V |
SDI Interface Mode Select 1 / Auto Sleep Control |
|
SDI_MF2_MUTE |
N12 |
1.8 V |
SDI Interface Mode Select 2 / Output Mute |
|
SDI_TX_SD_HDN |
N13 |
1.8 V |
SDI Interface TX Signal Detect |
|
SENSE_CS0N |
D9 |
2.5 V |
SPI Interface Chip Select |
|
SENSE_SCK |
B9 |
2.5 V |
SPI Interface Clock |
|
SENSE_SDI |
B3 |
2.5 V |
SPI Interface Serial Data In |
|
SENSE_SDO |
C9 |
2.5 V |
SPI Interface Serial Data Out |
|
SENSE_SMB_CLK |
A15 |
2.5 V |
I2C Interface Clock |
|
SENSE_SMB_DATA |
B13 |
2.5 V |
I2C Interface Data |
|
SI516_FS |
C5 |
2.5 V |
Silicon Labs SI516 Clock Device Frequency Select |
|
SI570_EN |
A10 |
2.5 V |
Si570 programmable clock enable |
|
TSENSE_ALERTN |
B14 |
2.5 V |
MAX1619 device Temperature Sense Alert Signal |
|
USB_CFG0 |
M4 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG1 |
M3 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG2 |
K2 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG3 |
K5 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG4 |
L1 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG5 |
L2 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG6 |
K3 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG7 |
M2 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG8 |
L4 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG9 |
L3 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG10 |
N1 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG11 |
N2 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG12 |
M1 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG13 |
N3 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_CFG14 |
P2 |
1.8 V |
On-board USB-Blaster II interface (reserved for future use) |
|
USB_M5_CLK |
H5 |
1.8 V |
On-board USB-Blaster II interface clock |
|
ED8101_ALERT |
B8 |
2.5 V |
ED8101 Alert signal |
|
ED8101_SCL |
A8 |
2.5 V |
ED8101 I2C clock signal |
|
ED8101_SDA |
A9 |
2.5 V |
ED8101 I2C data signal |
FPGA Configuration
Configuring the FPGA Using Programmer
- The Quartus Programmer and the USB-Blaster II driver are installed on the host computer.
- The micro-USB cable is connected to the FPGA development board.
- Power to the board is on, and no other applications that use the JTAG chain are running.
- Start the Quartus Programmer.
- Click Auto Detect to display the devices in the JTAG chain.
- Click Change File and select the path to the desired .sof.
- Turn on the Program/Configure option for the added file.
- Click Start to download the selected file to the FPGA. Configuration is complete when the progress bar reaches 100%.
Status Elements
The Arria 10 GX FPGA development board includes status LEDs.
|
Board Reference |
Schematic Signal Name |
I/O Standard |
|---|---|---|
|
D16 |
MAX_ERROR |
2.5 V |
|
D15 |
MAX_LOAD |
2.5 V |
|
D17 |
MAX_CONF_DONE |
2.5 V |
|
D1 |
FMCA_TX_LED |
1.8 V |
|
D2 |
FMCA_RX_LED |
1.8 V |
|
D12 |
PGM_LED0 |
2.5 V |
|
D13 |
PGM_LED1 |
2.5 V |
|
D14 |
PGM_LED2 |
2.5 V |
|
D11 |
FMCA_PRSNTn |
1.8 V |
|
D18 |
FMCB_TX_LED |
1.8 V |
|
D20 |
FMCB_RX_LED |
1.8 V |
|
D21 |
FMCB_PRSNTn |
1.8 V |
|
D34 |
PCIE_LED_X1 |
1.8 V |
|
D35 |
PCIE_LED_X4 |
1.8 V |
|
D36 |
PCIE_LED_X8 |
1.8 V |
|
D37 |
PCIE_LED_G2 |
1.8 V |
|
D38 |
PCIE_LED_G3 |
1.8 V |
User Input/Output
User-Defined Push Buttons
The Arria 10 GX FPGA development board includes user-defined push buttons. When you press and hold down the button, the device pin is set to logic 0; when you release the button, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons.
|
Board Reference |
Schematic Signal Name |
FPGA Pin Number |
I/O Standard |
|---|---|---|---|
|
S1 |
USER_PB2 |
U11 |
1.8 V |
|
S2 |
USER_PB1 |
U12 |
1.8 V |
|
S3 |
USER_PB0 |
T12 |
1.8 V |
|
S4 |
CPU_RESETn |
BD27 |
1.8 V |
|
S5 |
PGM_SEL |
— |
2.5 V |
|
S6 |
PGM_CONFIG |
— |
2.5 V |
|
S7 |
MAX_RESETn |
— |
2.5 V |
User-Defined DIP Switch
The Arria 10 GX FPGA development board includes a set of eight-pin DIP switch. There are no board-specific functions for these switches. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected.
|
Board Reference |
Schematic Signal Name |
FPGA Pin Number |
I/O Standard |
|---|---|---|---|
|
1 |
USER_DIPSW0 |
A24 |
1.8-V |
|
2 |
USER_DIPSW1 |
B23 |
1.8-V |
|
3 |
USER_DIPSW2 |
A23 |
1.8-V |
|
4 |
USER_DIPSW3 |
B22 |
1.8-V |
|
5 |
USER_DIPSW4 |
A22 |
1.8-V |
|
6 |
USER_DIPSW5 |
B21 |
1.8-V |
|
7 |
USER_DIPSW6 |
C21 |
1.8-V |
|
8 |
USER_DIPSW7 |
A20 |
1.8-V |
User-Defined LEDs
The Arria 10 GX FPGA development board includes a set of eight pairs user-defined LEDs. The LEDs illuminate when a logic 0 is driven, and turns off when a logic 1 is driven. There are no board-specific functions for these LEDs.
| Board Reference | Schematic Signal Name | FPGA Pin Number | I/O Standard |
|---|---|---|---|
| D10 | USER_LED_G0 | L28 | 1.8 V |
| D9 | USER_LED_G1 | K26 | 1.8 V |
| D8 | USER_LED_G2 | K25 | 1.8 V |
| D7 | USER_LED_G3 | L25 | 1.8 V |
| D6 | USER_LED_G4 | J24 | 1.8 V |
| D5 | USER_LED_G5 | A19 | 1.8 V |
| D4 | USER_LED_G6 | C18 | 1.8 V |
| D3 | USER_LED_G7 | D18 | 1.8 V |
| D10 | USER_LED_R0 | L27 | 1.8 V |
| D9 | USER_LED_R1 | J26 | 1.8 V |
| D8 | USER_LED_R2 | K24 | 1.8 V |
| D7 | USER_LED_R3 | L23 | 1.8 V |
| D6 | USER_LED_R4 | B20 | 1.8 V |
| D5 | USER_LED_R5 | C19 | 1.8 V |
| D4 | USER_LED_R6 | D19 | 1.8 V |
| D3 | USER_LED_R7 | M23 | 1.8 V |
Character LCD
The Arria 10 GX FPGA development board includes a single 10-pin 0.1" pitch single-row header that interfaces to a 16 character × 2 line Lumex LCD display. The LCD has a 10-pin receptacle that mounts directly to the board's 10-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or other purposes.
| Board Reference | Schematic Signal Name | FPGA Pin Number | I/O Standard | Description |
|---|---|---|---|---|
| 5 | SPI_SS_DISP / DISP_SPISS | BA35 | 1.8 V | SPI slave select (only used in SPI mode) |
| 7 | I2C_SCL_DISP / DISP_I2C_SCL | AW33 | 1.8 V | I2C LCD serial clock |
| 8 | I2C_SDA_DISP / DISP_I2C_SDA | AY34 | 1.8 V | I2C LCD serial data |
DisplayPort
The Arria 10 GX FPGA development board includes a DisplayPort connector.
|
Board Reference |
Schematic Signal Name |
FPGA Pin Number |
I/O Standard |
Description |
|---|---|---|---|---|
|
13 |
DP_3P3V_CONFIG1 |
AK31 |
1.8 V |
— |
|
14 |
DP_3P3V_CONFIG2 |
AK32 |
1.8 V |
— |
|
18 |
DP_3P3V_HOT_PLUG |
AM30 |
1.8 V |
Hot plug detect |
|
17 |
DP_AUX_CN |
AM35 |
LVDS |
Auxiliary channel (negative) |
|
15 |
DP_AUX_CP |
AN34 |
LVDS |
Auxiliary channel (positive) |
|
3 |
DP_ML_LANE_CN0 |
AP43 |
High Speed Differential I/O |
Lane 0 (negative) |
|
6 |
DP_ML_LANE_CN1 |
AM43 |
High Speed Differential I/O |
Lane 1 (negative) |
|
9 |
DP_ML_LANE_CN2 |
AH43 |
High Speed Differential I/O |
Lane 2 (negative) |
|
12 |
DP_ML_LANE_CN3 |
AF43 |
High Speed Differential I/O |
Lane 3 (negative) |
|
1 |
DP_ML_LANE_CP0 |
AP44 |
High Speed Differential I/O |
Lane 0 (positive) |
|
4 |
DP_ML_LANE_CP1 |
AM44 |
High Speed Differential I/O |
Lane 1 (positive) |
|
7 |
DP_ML_LANE_CP2 |
AH44 |
High Speed Differential I/O |
Lane 2 (positive) |
|
10 |
DP_ML_LANE_CP3 |
AF44 |
High Speed Differential I/O |
Lane 3 (positive) |
|
19 |
DP_RTN |
AL33 |
High Speed Differential I/O |
Return for power |
SDI Video Input/Output Ports
The Arria 10 GX FPGA development board includes a SDI video port, which consists of a M23428G-33 cable driver and a M23544G-14 cable equalizer. The PHY devices from Macom interface to single-ended SMB connectors.
|
SD_HD Input |
Supported Output Standards |
Rise Time |
|---|---|---|
|
0 |
SMPTE 424M, SMPTE 292M |
Faster |
|
1 |
SMPTE 259M |
Slower |
|
Board Reference |
Schematic Signal Name |
FPGA Pin Number |
I/O Standard |
|---|---|---|---|
|
14 |
SDI_AVDD |
— |
— |
|
2 |
SDI_AVDD |
— |
— |
|
7 |
SDI_AVDD |
— |
— |
|
9 |
SDI_SD_HDN |
AW34 |
1.8 V |
|
5 |
SDI_TX_RSET |
— |
— |
|
1 |
SDI_TXCAP_N |
D43 |
High Speed Differential I/O |
|
16 |
SDI_TXCAP_P |
D44 |
High Speed Differential I/O |
|
10 |
SDI_TXDRV_N |
— |
— |
|
11 |
SDI_TXDRV_P |
— |
— |
|
Cable Type |
Data Rate (Mbps) |
Maximum Cable Length (m) |
|---|---|---|
|
Belden 1694A |
270 |
400 |
|
Belden 1694A |
1485 |
140 |
|
Belden 1694A |
2970 |
120 |
|
Board Reference |
Schematic Signal Name |
FPGA Pin Number |
I/O Standard |
|---|---|---|---|
|
9 |
AGCN |
— |
— |
|
8 |
AGXP |
— |
— |
|
10 |
MF0_BYPASS |
AW32 |
1.8 V |
|
19 |
MF1_AUTO_SLEEP |
AY32 |
1.8 V |
|
21 |
MF2_MUTE |
AY35 |
1.8 V |
|
22 |
MF3_XSD |
— |
— |
|
6 |
MODE_SEL |
— |
— |
|
11 |
MUTEREF |
— |
— |
|
4 |
SDI_EQIN_N1 |
— |
— |
|
3 |
SDI_EQIN_P1 |
— |
— |
|
14 |
SDO_N / SDI_RX_N |
H39 |
High Speed Differential I/O |
|
15 |
SDO_P / SDI_RX_P |
H40 |
High Speed Differential I/O |
Clock Circuitry
On-Board Oscillators
| Source | Schematic Signal Name | Frequency | I/O Standard | Arria 10 FPGA Pin Number | Application |
|---|---|---|---|---|---|
| U14 | REFCLK_SMA_P | 302.083333 MHz | 1.8 V LVDS | N37 | Transceiver reference clocks Bank-1H |
| REFCLK_SMA_N | 1.8 V LVDS | N38 | |||
| REFCLK_FMCB_P | 625 MHz | 1.8 V LVDS | AA8 | FMC B reference clocks | |
| REFCLK_FMCB_N | 1.8 V LVDS | AA7 | |||
| REFCLK_FMCA_P | 625 MHz | 1.8 V LVDS | AN8 | FMC A reference clocks | |
| REFCLK_FMCA_N | 1.8 V LVDS | AN7 | |||
| PCIE_OB_REFCLK_P | 100 MHz | 1.8 V LVDS | AN37 | PCIE reference clocks | |
| PCIE_OB_REFCLK_N | 1.8 V LVDS | AN38 | |||
| U26 | CLK_EMI_P | 133.33 MHz | 1.8 V LVDS | F34 | EMI reference clocks |
| CLK_EMI_N | 1.8 V LVDS | F35 | |||
| REFCLK_QSFP_P | 644.53125 MHz | 1.8 V LVDS | R37 | QSFP reference clocks | |
| REFCLK_QSFP_N | 1.8 V LVDS | R38 | |||
| REFCLK_SFP_P | 644.53125 MHz | 1.8 V LVDS | AA37 | SFP reference clocks | |
| REFCLK_SFP_N | 1.8 V LVDS | AA38 | |||
| REFCLK_DP_P | 270 MHz | 1.8 V LVDS | AC37 | Display port (DP) reference clocks | |
| REFCLK_DP_N | 1.8 V LVDS | AC38 | |||
| X1 | REFCLK_SDI_P | 148.35 MHz | 2.5 V | L37 | SDI reference clocks |
| REFCLK_SDI_N | 2.5 V | L38 | |||
| X2 | CLK_125_P | 125 MHz | 2.5 V | BD24 | 125 MHz reference clocks for Arria 10 FPGA |
| CLK_125_N | 2.5 V | BC24 | |||
| X3 | 100M_OSC_P | 100 MHz | LVDS | AR36, F23, AG37, AC8 | Programmable Oscillator default 100MHz |
| 100M_OSC_N | LVDS | AR37, G23, AG38, AC7 | |||
| U53 | MV_CLK_50 | 50 MHz | 1.8 V | - | MAX V System Controller clock |
| CLK_50 | 1.8 V | AU33 | Arria 10 FPGA reference clock |
Off-Board Clock I/O
The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.
| Source | Schematic Signal Name | I/O Standard | Arria 10 FPGA Pin Number | Description |
|---|---|---|---|---|
| J6 | CLKIN_SMA | 2.5 V | - | SMA clock input |
| Source | Schematic Signal Name | I/O Standard | Arria 10 FPGA Pin Number | Description |
|---|---|---|---|---|
| J7 | SMA_CLK_OUT | 1.8 V | E24 | SMA clock output |
| J16 | SMA_TX_P | 1.8 V | C42 | SMA transfer clocks |
| J15 | SMA_TX_N | 1.8 V | C41 |
Components and Interfaces
PCI Express
The Arria 10 GX FPGA development board is designed to fit entirely into a PC motherboard with a ×8 PCI Express slot that can accommodate a full height long form factor add-in card. This interface uses the Arria 10 GX FPGA's PCI Express hard IP block, saving logic resources for the user logic application. The PCI express edge connector has a presence detect feature to allow the motherboard to determine if a card is installed.
The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 to ×8 by using Altera's PCIe MegaCore IP. You can also configure this board to a ×1, ×4, or ×8 interface through a DIP switch that connects the PRSNTn pins for each bus width.
The PCI Express edge connector has a connection speed of 2.5 Gbps/lane for a maximum of 20 Gbps full-duplex (Gen1), 5.0 Gbps/lane for a maximum of 40 Gbps full-duplex (Gen2), or 8.0 Gbps/lane for a maximum of 64 Gbps full-duplex (Gen3).
The power for the board can be sourced entirely from the PC host when installed into a PC motherboard with the PC's 2x4 ATX auxilary power connected to the 12V ATX input (J4) of the Arria 10 development board. Although the board can also be powered by a laptop power supply for use on a lab bench, Altera recommends that you do not power up from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or back-current from one supply to the other.
The PCIE_REFCLK_P signal is a 100 MHz differential input that is driven from the PC motherboard on to this board through the edge connector. This signal connects directly to a Arria 10 GX FPGA REFCLK input pin pair using DC coupling. This clock is terminated on the motherboard and therefore, no on-board termination is required. This clock can have spread-spectrum properties that change its period between 9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL). The JTAG and SMB are optional signals in the PCI Express specification. Therefore, the JTAG signal loopback from PCI Express TDI to PCI Express TDO and are not used on this board. The SMB signals are wired to the Arria 10 GX FPGA but are not required for normal operation.
| Receive bus | Receive bus | FPGA Pin Number | I/O Standard | Description |
|---|---|---|---|---|
|
A11 |
PCIE_EDGE_PERSTN |
BC30 |
1.8 V |
Reset |
|
A14 |
PCIE_EDGE_REFCLK_N |
AL38 |
LVDS |
Motherboard reference clock |
|
A13 |
PCIE_EDGE_REFCLK_P |
AL37 |
LVDS |
Motherboard reference clock |
|
B5 |
PCIE_EDGE_SMBCLK |
BD29 |
1.8 V |
SMB clock |
|
B6 |
PCIE_EDGE_SMBDAT |
AU37 |
1.8 V |
SMB data |
|
A1 |
PCIE_PRSNT1N |
— |
— |
Link with DIP switch |
|
B17 |
PCIE_PRSNT2N_X1 |
— |
— |
Link with DIP switch |
|
B31 |
PCIE_PRSNT2N_X4 |
— |
— |
Link with DIP switch |
|
B48 |
PCIE_PRSNT2N_X8 |
— |
— |
Link with DIP switch |
|
B15 |
PCIE_RX_N0 |
AT39 |
High Speed Differential I/O |
Receive bus |
|
B20 |
PCIE_RX_N1 |
AP39 |
High Speed Differential I/O |
Receive bus |
|
B24 |
PCIE_RX_N2 |
AN41 |
High Speed Differential I/O |
Receive bus |
|
B28 |
PCIE_RX_N3 |
AM39 |
High Speed Differential I/O |
Receive bus |
|
B34 |
PCIE_RX_N4 |
AL41 |
High Speed Differential I/O |
Receive bus |
|
B38 |
PCIE_RX_N5 |
AK39 |
High Speed Differential I/O |
Receive bus |
|
B42 |
PCIE_RX_N6 |
AJ41 |
High Speed Differential I/O |
Receive bus |
|
B46 |
PCIE_RX_N7 |
AH39 |
High Speed Differential I/O |
Receive bus |
|
B14 |
PCIE_RX_P0 |
AT40 |
High Speed Differential I/O |
Receive bus |
|
B19 |
PCIE_RX_P1 |
AP40 |
High Speed Differential I/O |
Receive bus |
|
B23 |
PCIE_RX_P2 |
AN42 |
High Speed Differential I/O |
Receive bus |
|
B27 |
PCIE_RX_P3 |
AM40 |
High Speed Differential I/O |
Receive bus |
|
B33 |
PCIE_RX_P4 |
AL42 |
High Speed Differential I/O |
Receive bus |
|
B37 |
PCIE_RX_P5 |
AK40 |
High Speed Differential I/O |
Receive bus |
|
B41 |
PCIE_RX_P6 |
AJ42 |
High Speed Differential I/O |
Receive bus |
|
B45 |
PCIE_RX_P7 |
AH40 |
High Speed Differential I/O |
Receive bus |
|
A17 |
PCIE_TX_CN0 |
BB43 |
High Speed Differential I/O |
Transmit bus |
|
A22 |
PCIE_TX_CN1 |
BA41 |
High Speed Differential I/O |
Transmit bus |
|
A26 |
PCIE_TX_CN2 |
AY43 |
High Speed Differential I/O |
Transmit bus |
|
A30 |
PCIE_TX_CN3 |
AW41 |
High Speed Differential I/O |
Transmit bus |
|
A36 |
PCIE_TX_CN4 |
AV43 |
High Speed Differential I/O |
Transmit bus |
|
A40 |
PCIE_TX_CN5 |
AU41 |
High Speed Differential I/O |
Transmit bus |
|
A44 |
PCIE_TX_CN6 |
AT43 |
High Speed Differential I/O |
Transmit bus |
|
A48 |
PCIE_TX_CN7 |
AR41 |
High Speed Differential I/O |
Transmit bus |
|
A16 |
PCIE_TX_CP0 |
BB44 |
High Speed Differential I/O |
Transmit bus |
|
A21 |
PCIE_TX_CP1 |
BA42 |
High Speed Differential I/O |
Transmit bus |
|
A25 |
PCIE_TX_CP2 |
AY44 |
High Speed Differential I/O |
Transmit bus |
|
A29 |
PCIE_TX_CP3 |
AW42 |
High Speed Differential I/O |
Transmit bus |
|
A35 |
PCIE_TX_CP4 |
AV44 |
High Speed Differential I/O |
Transmit bus |
|
A39 |
PCIE_TX_CP5 |
AU42 |
High Speed Differential I/O |
Transmit bus |
|
A43 |
PCIE_TX_CP6 |
AT44 |
High Speed Differential I/O |
Transmit bus |
|
A47 |
PCIE_TX_CP7 |
AR42 |
High Speed Differential I/O |
Transmit bus |
|
B11 |
PCIE_WAKEN_R |
AY29 |
1.8 V |
Wake signal |
10/100/1000 Ethernet PHY
The Arria® 10 GX FPGA development board supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs SGMII using the Arria 10 GX FPGA LVDS pins in Soft-CDR mode at 1.25 Gbps transmit and receive. In 10-Mb or 100-Mb mode, the SGMII interface still runs at 1.25 GHz but the packet data is repeated 10 or 100 times. The MAC function must be provided in the FPGA for typical networking applications.
The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25 MHz reference clock driven from a dedicated oscillator. The PHY interfaces to a HALO HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper lines with Ethernet traffic.
|
Board Reference (U15) |
Schematic Signal Name |
FPGA Pin Number |
I/O Standard | Description |
|---|---|---|---|---|
|
23 |
ENET_2P5V_INTN |
AG13 |
1.8 V |
Management bus interrupt |
|
25 |
ENET_2P5V_MDC |
AF13 |
1.8 V |
Management bus data clock |
|
24 |
ENET_2P5V_MDIO |
AL18 |
1.8 V |
Management bus data |
|
28 |
ENET_2P5V_RESETN |
AW23 |
1.8 V |
Device reset |
|
59 |
ENET_LED_LINK10 |
— |
2.5 V |
10-Mb link LED |
|
76 |
ENET_LED_LINK10 |
— |
2.5 V |
10-Mb link LED |
|
74 |
ENET_LED_LINK100 |
— |
2.5 V |
100-Mb link LED |
|
60 |
ENET_LED_LINK1000 |
— |
2.5 V |
1000-Mb link LED |
|
73 |
ENET_LED_LINK1000 |
— |
2.5 V |
1000-Mb link LED |
|
58 |
ENET_LED_RX |
— |
2.5 V |
RX data active LED |
|
69 |
ENET_LED_RX |
— |
2.5 V |
RX data active LED |
|
68 |
ENET_LED_TX |
— |
2.5 V |
TX data active LED |
|
30 |
ENET_RSET |
AW23 |
1.8 V |
Device reset |
|
75 |
ENET_RX_N |
AW24 |
LVDS |
SGMII receive channel |
|
77 |
ENET_RX_P |
AV24 |
SGMII receive channel |
|
|
81 |
ENET_TX_N |
BD23 |
SGMII transmit channel |
|
|
82 |
ENET_TX_P |
BC23 |
SGMII transmit channel |
|
|
55 |
ENET_XTAL_25MHZ |
— |
2.5 V |
25-MHz RGMII transmit clock |
|
31 |
MDI_N0 |
— |
Media dependent interface |
|
|
34 |
MDI_N1 |
— |
||
|
41 |
MDI_N2 |
— |
||
|
43 |
MDI_N3 |
— |
||
|
29 |
MDI_P0 |
— |
||
|
33 |
MDI_P1 |
— |
||
|
39 |
MDI_P2 |
— |
||
|
42 |
MDI_P3 |
— |
HiLo External Memory Interface
This section describes the Arria 10 GX FPGA development board’s external memory interface support and also their signal names, types, and connectivity relative to the Arria 10 GX FPGA.
The HiLo connector supports plugins the following memory interfaces:
- DDR3 x72 (included in the kit)
- DDR4 x72 (included in the kit)
- RLDRAM3 x36 (included in the kit)
- QDR IV x36 (not included. Contact your local Altera sales representative for ordering and availability)
|
Board Reference |
Schematic Signal Name |
FPGA Pin Number |
I/O Standard |
|---|---|---|---|
|
F1 |
MEM_ADDR_CMD0 |
M32 |
1.5 V |
|
H1 |
MEM_ADDR_CMD1 |
L32 |
1.5 V |
|
F2 |
MEM_ADDR_CMD2 |
N34 |
1.5 V |
|
G2 |
MEM_ADDR_CMD3 |
M35 |
1.5 V |
|
H2 |
MEM_ADDR_CMD4 |
L34 |
1.5 V |
|
J2 |
MEM_ADDR_CMD5 |
K34 |
1.5 V |
|
K2 |
MEM_ADDR_CMD6 |
M33 |
1.5 V |
|
G3 |
MEM_ADDR_CMD7 |
L33 |
1.5V |
|
J3 |
MEM_ADDR_CMD8 |
J33 |
1.5 V |
|
L3 |
MEM_ADDR_CMD9 |
J32 |
1.5 V |
|
E4 |
MEM_ADDR_CMD10 |
H31 |
1.5 V |
|
F4 |
MEM_ADDR_CMD11 |
J31 |
1.5 V |
|
G4 |
MEM_ADDR_CMD12 |
H34 |
1.5 V |
|
H4 |
MEM_ADDR_CMD13 |
H33 |
1.5 V |
|
J4 |
MEM_ADDR_CMD14 |
G32 |
1.5 V |
|
K4 |
MEM_ADDR_CMD15 |
E32 |
1.5 V |
|
M1 |
MEM_ADDR_CMD16 |
F33 |
1.5 V |
|
M2 |
MEM_ADDR_CMD17 |
G35 |
1.5 V |
|
N2 |
MEM_ADDR_CMD18 |
H35 |
1.5 V |
|
L4 |
MEM_ADDR_CMD19 |
G33 |
1.5 V |
|
P5 |
MEM_ADDR_CMD20 |
U33 |
1.5 V |
|
M5 |
MEM_ADDR_CMD21 |
T33 |
1.5 V |
|
P1 |
MEM_ADDR_CMD22 |
R34 |
1.5 V |
|
R4 |