Intel FPGA and Programmable Devices / SoCs / Portfolio / Intel® Arria® 10 SoC FPGAs Support

Intel® Arria® 10 SoC FPGAs Support

  • Intel® Arria® 10 I/O Timing Spreadsheet
  • All Packaging Specifications and Dimensions
  • External Memory Interface Pin Information
  • Arria 10 SX Device Errata
  • Known Arria 10 Issues
  • Arria 10 SoC HPS Address Map and Register Definitions (HTML)
  • Arria 10 SoC HPS Address Map and Register Definitions (ZIP)
  • Pin Connection Guidelines
  • Device Pin-Outs
  • BSDL Files
  • Board Design Guidelines
  • Arria 10 SoC HPS Supported Flash Devices 
  • Arria 10 SoC Device Design Guidelines 

快速链接

  • Documentation: Pin-Out Files for Intel FPGA Devices

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Power and Thermal Management
  • AN 711: Power Reduction Features in Arria 10 Devices
  • Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
    Power Delivery Network (PDN) Tool 2.0 for Stratix® V, Arria V, Arria II GZ, Cyclone® V, and Cyclone IV Devices
    Power Delivery Network (PDN) Tool 2.0 for Stratix and Arria 10 Devices
Design Guidelines
  • AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
  • AN 738: Arria 10 Device Design Guidelines
     
End Applications
  • AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
  • OTN Family | 200G P-OTS Any-Rate Mapper | TPOC226 (ver 1.0, Mar 2014, 607 KB)
    (SoftSilicon function)
  • OTN Family | 400G Transponder / Muxponder | TPO516 (ver 1.0, Mar 2014, 469 KB)
    (SoftSilicon function)
General Device Documentation
  • Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
  • Differences Among Intel SoC Device Families
  • Arria 10 SoC Boot User Guide
  • Arria 10 SoC Secure Boot User Guide
  • Arria 10 SoC Virtual Platform User Guide
  • Arria 10 SoC Virtual Platform Release Notes

Related Links

  • Intel SoC FPGA Overview
  • Architecture Matters