| 文件 | 發佈日期 | Filter | Doc Type Filter | Collections Filter |
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- Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions (ver 1.0, Nov 2011, 589 KB)
- Arria II and Arria V PowerPlay Early Power Estimator
(Final)
PowerPlay Early Power Estimator User Guide
- An Independent Evaluation of Floating-Point DSP Energy Efficiency on Altera 28 nm FPGAs
(BDTI)
- AN 657: Thermal Management and Mechanical Handling for Altera TCFCBGA Devices
- Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
Power Delivery Network (PDN) Tool 2.0 for Stratix® V, Arria V, Arria II GZ, Cyclone® V, and Cyclone IV Devices (5 MB)
Power Delivery Network (PDN) Tool 2.0 for Arria 10 Devices (3 MB)
- Meeting the Low Power Imperative at 28 nm
- AN 456: PCI Express* High Performance Reference Design
- AN 696: Using the JESD204B MegaCore Function in Arria V Devices
- Altera JESD204B MegaCore Function and ADI AD9250 Hardware Checkout Report
AN 696 Reference Design Example (3 MB)
- Arria V Avalon®-MM Interface for PCIe* Solutions User Guide
- Arria V Avalon-ST Interface for PCIe Solutions User Guide
- Arria V Hard IP for PCI Express User Guide
- AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Altera FPGAs
- AN 668: Serial Digital Interface Reference Design for Stratix V GX and Arria V GX Devices
Arria V GX Design Files (2 MB)
Stratix V GX Design Files (1 MB)
- AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
- AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
- AN 653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core
AN 653_Reference_Design_File (346 KB)
- Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide
- Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide
- Early SSN Estimator User Guide for Altera Programmable Devices
Arria V Early SSN Estimator (528 KB)
- V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
- AN 652: Arria V Timing Optimization Guidelines
- Achieving SerDes Interoperability on Altera's 28 nm FPGAs Using Introspect ESP (Introspect)
- AN 662: Arria V and Cyclone V Design Guidelines
- AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
AN 676 Reference Design Example
- An Independent Evaluation of Floating-Point DSP Energy Efficiency on Altera 28 nm FPGAs
- Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP
- Real-Time Challenges and Opportunities in SoCs
- Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach
- Tips and Techniques for 28 nm Design Optimization
- Intel FPGA Product Catalog
- Arria V GT FPGA Development Board Reference Manual
- Arria V GT FPGA Development Kit User Guide
- Arria V GX FPGA Development Board Reference Manual
- Arria V GX FPGA Development Kit User Guide
- Arria V GX Starter Board Reference Manual
- Arria V GX Starter Kit User Guide
- Arria V SoC Development Board Reference Manual
- Arria V SoC Development Kit User Guide
- AN 717: Nios® II Gen2 Hardware Development Tutorial
- A Validated Methodology for Designing Safe Industrial Systems on a Chip
- Altera and Escape Communications' Microwave Modem Solution
- Altera's 28 nm Device Portfolio
- AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
- Broadcast Design Solutions from Altera
- Optimize Motor Control Designs with an Integrated FPGA Design Flow
- OTN Family | 200G P-OTS Any-Rate Mapper | TPOC226 (SoftSilicon function)
- OTN Family | 400G Transponder / Muxponder | TPO516 (SoftSilicon function)
- Reducing Development Time for Advanced Medical Endoscopy Systems with an FPGA-Based Approach
- Differences Among Intel SoC Device Families
- Altera QAM Design Solution for HD Video
- Intel User-Customizable SoC FPGAs
- Designing Polyphase DPD Solutions with 28-nm FPGAs
- FPGA-Adaptive Software Debug and Performance Analysis
- Implementing Efficient Low-Power PCIe Interfaces with Low-Cost FPGAs
- Industrial Motor Drive on a Single FPGA
- Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP
- Optimize Power and Cost with Altera’s Diversified 28-nm Device Portfolio
- Robust Image Format Conversion Solutions