The Stratix® 10 Support page contains information to help you get started with Stratix 10 designs, including videos, documentation, and training courses.
- Stratix 10: The Most Powerful, Most Efficient FPGA for Signal Processing (PDF)
- A New FPGA Architecture and Leading-Edge FinFET Process Technology Promise to Meet Next-Generation System Requirements (PDF)
- Understanding How the New HyperFlex Architecture Enables Next-Generation High-Performance Systems (PDF)
- Using Quartus® Prime Software to Maximize Performance in the HyperFlex™ Architecture (PDF)
- Leveraging HyperFlex Architecture in Stratix 10 Devices to Achieve Maximum Power Reduction (PDF)
- Enabling Next-Generation Platforms Using Intel's 3D System-in-Package Technology (PDF)
- Stratix 10 Secure Device Manager Provides Best-in-Class FPGA and SoC Security (PDF)
- The Breakthrough Advantage for FPGAs with Tri-Gate Technology (PDF)
- Meeting the Performance and Power Imperative of the Zettabyte Era with Generation 10 (PDF)
- Expect a Breakthrough Advantage in Next-Generation FPGAs (PDF)
- Stratix 10 Device Design Guidelines
- AN 114: Board Design Guidelines for Intel Programmable Device Packages
- AN 778: Stratix 10 Transceiver Usage
- AN 766: Stratix 10 Devices, High Speed Signal Interface Layout Design Guideline
- AN 790: PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces
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Free HyperFlex Online Training
| Course Title | Description |
|---|---|
| Stratix 10 HyperFlex Architecture Overview | Learn about the new HyperFlex core architecture, featured in Stratix 10 devices, that enables your designs to achieve 2X performance compared to previous-generation devices. |
| Quartus Prime Hyper-Aware Design Flow | Learn the new features of the Quartus Prime software flow that help you to take advantage of the new Stratix 10 HyperFlex architecture. |
| Using Fast Forward Compile | Learn how to use the new Quartus Prime software Fast Forward Compile feature to perform rapid design performance exploration to achieve your target performance goals. |
| Introduction to Hyper-Retiming | Learn how Hyper-Retiming works with the HyperFlex architecture and how it is different from conventional FPGA retiming strategies. |
| Eliminating Barriers to Hyper-Retiming | Learn what design situations and coding styles prevent you from achieving the maximum performance gains with Hyper-Retiming in the Stratix 10 HyperFlex architecture. |
| Introduction to Hyper-Pipelining | Learn how Hyper-Pipelining works with the HyperFlex architecture and how it is different from conventional FPGA pipelining strategies. |
| Understanding Critical Chains | Learn to analyze critical chains and how to solve them to achieve higher clock speeds. |
| Introduction to Hyper-Optimization | Learn how Hyper-Optimization works and how to determine if it is required to achieve your target design goals. |
| Hyper-Optimization Techniques 1: Loop Analysis and Solutions | Learn about the typical types of performance bottlenecks caused by loops in FPGA designs and basic strategies to prevent loops from limiting design performance in Stratix 10 devices. |
| Hyper-Optimization Techniques 2: Pre-Computation | Learn the methods and techniques behind pre-computation to reduce the impact of loops on design performance in Stratix 10 devices. |
| Hyper-Optimization Techniques 3: Shannon’s Decomposition | Learn how the special optimization technique, Shannon’s Decomposition, can be used to minimize the impact of loops for designs targeting Stratix 10 devices. |
HyperFlex Instructor-Led/Virtual Training
| Course Title | Description |
|---|---|
| Performance Optimization with Stratix 10 HyperFlex Architecture | In the Performance Optimization with Stratix 10 HyperFlex Architecture course, you will learn Quartus Prime software features and some basic design techniques that will enable your designs to take advantage of the Stratix 10 HyperFlex architecture. In the training, you will learn two steps to improving your performance with the HyperFlex architecture, with each step allowing you to move you up the performance curve. |
| Advanced Optimization with Stratix 10 HyperFlex Architecture | In the Advanced Optimzation with Stratix 10 HyperFlex Architecture course, you will learn design techniques that will enable you to unleash the full potential of the Stratix 10 HyperFlex architecture. In the training, you will learn how to modify your coding style and logic structures and, as a result, allow your design to achieve clock rates of up to two times when compared to a non-optimized design, without changing overall design functionality. |