This simple example demonstrates the use of Intel read-only zip filing system and GNU debugger (GDB) host filing system. The example includes a zip filing system (.zip file) containing three text files. The filing system is first programmed into the hardware design's common flash interface (CFI) compliant flash using the Nios® II flash programmer. When you run the software, it opens two of the text files in the filing system, then prints them to STDOUT.
Using This Design Example
Download this example from the Intel FPGA Wiki section. Follow the instruction in the readme.txt file to run the example.
The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.
Hardware Requirements
This example requires the following devices to be present in the target hardware design:
STDOUTcomponent such as a UART or JTAG UART- CFI compliant flash component
You can run this software design example on the following Nios II hardware design examples:
Nios II Development Board, Stratix® II Edition:
- Standard
- Full Featured
Nios II Development Board, Stratix Professional Edition:
- Standard
- Full Featured
Nios II Development Board, Stratix Edition:
- Standard
- Full Featured
Nios II Development Board, Cyclone® II Edition:
- Standard
- Full Featured
Nios II Development Board, Cyclone Edition:
- Standard
- Full Featured
Design Examples Disclaimer
These design examples may only be used within Intel devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.