Intel® Quartus® Prime Software Suite

The Intuitive High-Performance Design Environment.

Overview

The revolutionary Intel® Quartus® Prime Design Software includes everything you need to design for Intel® FPGAs, SoCs, and complex programmable logic device (CPLD) from design entry and synthesis to optimization, verification, and simulation. Dramatically increased capabilities on devices with multi-million logic elements are providing designers with the ideal platform to meet next-generation design opportunities.

More details are available in the Quick-Start for Intel® Quartus® Prime Pro Edition Software and the Getting Started User Guide: Intel® Quartus® Prime Pro Edition.

Features and Downloads

To compare different Intel® Quartus® Prime Editions, please visit the getting started page.

What's New in 21.1

Intel® Quartus® Prime Pro Edition Software v21.1 supports the newest FPGA family:

Intel® Agilex™ FPGAs

The Intel® Agilex™ FPGA family leverages heterogeneous 3D system-in-package (SiP) technology to integrate Intel's first FPGA fabric built on 10 nm SuperFin Technology and 2nd Generation Intel® Hyperflex™ FPGA Architecture to deliver up to 45% higher performance (geomean vs. Intel® Stratix® 10)1 or up to 40% lower power1 for applications in Data Center, Networking, and Edge compute. Intel® Agilex™ SoC FPGAs also integrate the quad-core Arm Cortex-A53 processor to provide high system integration.

The Intel® Quartus® Prime Pro Edition Software v21.1 is an intuitive design environment that will help you meet your power and performance requirements and reduce your overall development effort. Features in the v21.1 release include:

  • Improvements for Intel® Agilex™ FPGA power, performance, runtime, memory, and logic utilization
  • New and improved Design Assistant design rules for synthesis, clock domain crossing (CDC), reset domain crossing (RDC), and timing
  • Hierarchical grouping of design rule checking (DRC)
  • Rule-tagging and filtering
  • DRC waiver mechanism
  • New ease-of-use reports for static timing analysis, design closure, synthesis, and undefined entities
  • More cross-probing and runtime improvements for reports
  • Locate SDC constraints in a file
  • Faster ECO compiles for post-fit tap targets in Signal Tap II Logic Analyzer
  • Flow-Resume feature
  • Improved GUI display for higher resolution monitors
  • Remote debug over Ethernet and PCI Express using Nios® II processor
  • Mark signals for debug (Beta) feature for register transfer level (RTL) development
  • Questa*-Intel® FPGA Edition Software (Beta Evaluation)
  • Updates to IP including
  • PCI Express
  • Interlaken
  • JESD
  • Transceivers
  • CPRI
  • ORAN
  • Ethernet

Free Hands-On Training

Register for FREE instructor-led classes for hands-on training to enhance your FPGA design skills.

  • The Intel® Quartus® Prime Software: Foundation
  • Using Intel® Stratix® 10 and Intel® Agilex™ SoC FPGAs
  • Introduction to the Platform Designer System Integration Tool
  • The Quartus Software Debug Tools
  • Timing Closure with Intel® Quartus® Prime Pro Software
  • Intel® Quartus® Prime Pro Software Timing Analysis
  • Using Intel® SoC FPGAs
  • Introduction to Verilog HDL
  • Advanced Verilog HDL Design Techniques
  • And more!

Documentation and Support

Find technical documentation, videos, and training courses for Intel® Quartus® Prime Design Software.

Subscribe to the Intel® FPGA Newsletter

Do you want the latest info about Intel® FPGAs, Programmable Accelerators, and power solutions? Looking for hot tips on training and tools? Click here to subscribe to the Intel Inside Edge Monthly Newsletter.

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產品與效能資訊

1

效能因使用情形、配置和其他因素而異。請造訪 www.Intel.com.tw/PerformanceIndex​​ 深入瞭解。

效能結果是依配置中所示日期的測試為準,且可能無法反映所有公開可用的安全性更新。請參閱設定檔配置的詳細資訊支援。沒有產品或元件能提供絕對的安全性。

您的成本和成果可能有所落差。