What's New in Intel® Quartus® Prime Software

Power and Performance

Intel® Agilex™ Device Support

The v20.3 release of the Intel® Quartus® Prime Pro Edition Software provides support for the Intel® Agilex™ device family of FPGAs. These innovative FPGAs leverage heterogeneous 3D system-in-package (SiP) technology to integrate Intel's first FPGA fabric built on 10nm process technology and 2nd Gen Intel® Hyperflex™ FPGA Architecture to deliver up to 40% higher performance or up to 40% lower power.1

Compilation Strategies

The compiler in Intel® Quartus® Prime Pro Edition Software is a fast, multi-faceted tool, allowing different compilation strategies that meet the designer's needs. In addition to standard compilation, which can give you a baseline for performance, there are other compilation options available:

  • Fast compile for small designs, introduced in 20.3, can be used to get quick compiles at the beginning of the development process when only a small portion of the design has been implemented.
  • High Effort compilation is used to make the compiler maximize its effort in order to get the best performance results out a of a design.
  • Fast Preservation compilations can be used with partitioned designs. Using a previously satisfactory compilation, Fast preservation simplifies the logic of a preserved partition to only the interface between the partition boundary and the rest of the design. The use of Fast Preservation reduces the compile time required for the preserved partition and thus the overall compile time.
  • Back Annotation is used in conjunction with seed sweeping to take the best compilation from run of different seeds and use that as the starting point for additional seed sweeping after fixing in place the results of pin-placement, clocks, RAMS, DSPs or a combination of these. The results are typically higher Fmax with less variation in results. Additionally, in 20.3, a GUI for Back Annotation has been provided to make it even easier to use.
  • ECO compilation is used when only minor changes are needed to an otherwise good compile. This flow was introduced in 19.3 and has been enhanced in each release. ECO compiles can provide a compilation speedup of 5x – 10x.2 It is also replacing the Rapid Recompile flow for post-fit SignalTap changes with significant compilation speedup. For 20.3 the ability to place flipflops has been added to allow for a richer set of ECO options when doing development and debug.

Additionally, there are many other parameters available to customize your compilation strategies to meet your specific requirements.

Power and Thermal Calculator

The Power and Thermal Calculator (PTC) supports Intel® Agilex™ and Stratix® 10 FPGA devices. For these devices it replaces the older Early Power Estimator. It can be used inside the Intel® Quartus® Prime Pro Edition Software or as a standalone tool. In 20.3 the look and feel of the PTC has been improved allowing greater customization of the layout as well as tooltips to describe various parameters in the PTC. In 20.3 the Thermals tab has been introduced for Agilex™ devices, allowing the designer to do thermal analysis for the design and providing a method to obtain cooling solutions under various conditions.

Ease of Use

Design Assistant / Snapshot Viewer

The Design Assistant and Snapshot Viewer are productivity tools meant for novice and advanced users. These tools enable faster design closure by reducing the number of design iterations required and speeds every iteration with targeted sanity checks and guidance at every stage of the compilation process. Learn more about Design Assistant and Snapshot Viewer with the provided video.

In Intel® Quartus® Prime Pro Edition Software 20.3 over 30 new rules have been added to Design Assistant covering memory instantiation, clock domain crossing, and reset domain crossing. Many of the Design Assistant rules support cross probing to timing reports to make it easier to investigate paths. Additionally, a new rule classification for "fatal rule violation" has been added that will stop the compilation if that rule is found to be violated. None of the DA rules are classified as "fatal", but any of the rules can be changed to fatal classification by the designer.

Platform Designer

Platform designer has been enhanced to improve GUI performance in Intel® Quartus® Prime Pro Edition Software 20.3. New features have been added to allow for parameter support for HDL and Blackbox IP instantiations as well as the ability to pass parameters via RTL. The Avalon Multi-Master Pipeline Bridge now supports passing the writeresponsevalid signal back to the master component. Additionally, the Avalon ST credit flow control, which provides higher performance through source flow control has been updated.

New Reports

Intel® Quartus® Prime Pro Edition Software continues to expand the rich set of compilation reports available. In the 20.3 release, several reports have been added or updated, including:

  • Report timing extra info
  • More information in Clock Transfers report
  • Route net of interest
  • Register spread
  • Hierarchical retiming restrictions
  • Pipelining information

This expanding portfolio of reports enables users to gather detailed information about routing, congestion, timing, tension, span, routing effort, and many other metrics that will provide rapid feedback for closing timing quickly.

Documentation and Support

Find technical documentation, videos, and training courses for Intel® Quartus® 
Prime Design Software.

產品與效能資訊

1

此一比較是根據 Intel® Agilex™ FPGA 和 SoC 系列相較於 Intel® Stratix® 10 FPGA 的模擬結果,其內容可能隨時變更。本文件包含在研發階段的產品、服務及/或程序之資訊。此處提供的所有資訊可能變更,恕不另行通知。請聯絡 Intel 代表以取得最新的預測、時間表、產品規格與藍圖。
Intel® 技術的功能與優勢取決於系統配置,而且可能需要支援的硬體、軟體或服務啟動才能使用。若想進一步瞭解,請前往 https://www.intel.com.tw,或洽 OEM 或零售商。沒有電腦系統能提供絕對的安全性。效能測試中使用的軟體與工作負載可能僅針對 Intel® 微處理器進行最佳化。

2

針對採用 Linux 64 作業系統的 Intel® Stratix® 10 1S280 裝置,為總計 28 種設計進行效能標竿測試。在網路清單變更後,對基準編譯時間與 ECO 編譯時間進行比較(8-2000,取決於 ECO 變更可採用的數值)。 效能測試等均使用特定的電腦系統、組件、軟體、作業及功能。任何有關上述條件的變更均可能導致不同結果。考慮購買時,為了充分評估效能,請參考其他資訊來源。如需有關效能與效能標竿結果的一般資訊,請參閱 http://www.intel.com.tw/benchmarks