What's New in Intel® Quartus® Prime Software

Power and Performance

Intel® Agilex™ Device Support

The v20.1 release of the Intel® Quartus® Prime Pro Edition Software provides support for the Intel® Agilex™ device family of FPGAs. These innovative FPGAs leverage heterogeneous 3D system-in-package (SiP) technology to integrate Intel's first FPGA fabric built on 10nm process technology and 2nd Gen Intel® Hyperflex™ FPGA Architecture to deliver up to 40% higher performance or up to 40% lower power.1

Compile Time

Continue seeing improvements in compile time for your Intel® FPGA designs compared to prior releases. Check out the Compile User Guide for additional tips on how to reduce compile times.

See a 33% compile time reduction when compared to Intel® Quartus® v18.1 for designs with high utilization.2

Avalon Streaming with Credit Flow Control

When creating high-performance system based on the Avalon ST protocol, credit flow control may help you close timing. Instead of control of flow through back-pressure from the sink, Avalon ST Credit provides a method for source flow control, providing higher performance and less congestion in difficult to fit designs using standard Avalon ST.

Intuitive Design Environment

Data-Centric User Interface

The Intel® Quartus® Prime Pro Edition Software user interface has been updated to create a more intuitive interface and modern look and feel, including wizards, reports, and analysis tools. But beyond this, the Intel® Quartus® Prime Software uses data gathered during the development and compilation process to provide:

  • Advanced analysis tasks leveraging multiple tools/features
  • Well defined paths for guided analyses
  • Deeper insight combining insights from different analysis views

Design Assistant / Snapshot Viewer

The Design Assistant and Snapshot Viewer are productivity tools meant for novice and advanced users. These tools enables faster design closure by reducing the number of design iterations required and speeds every iteration with targeted sanity checks and guidance at every stage of the compilation process. Learn more about Design Assistant and Snapshot Viewer with the provided video.

Unified Debug Toolkit

There are many different toolkits in Intel® Quartus® Prime Pro Edition Software, but they all have a different look and feel. The Unified Debug Toolkit (UDTK) is addressing this disparity. In v20.1 we have utilized the new framework to incorporate the various transceiver toolkits into the UDTK that highlights the new framework and incorporates the various transceiver toolkits into this new framework. In future releases the UDTK will incorporate all the debug toolkits together to give you a common flow for more intuitive debug.

Reduced Development Effort

Fast Preservation and ECO Flows

When coming to the end of the development your design may need some small changes to meet timing, but you don't want to do a full recompile. Fast Preservation and ECO flows provide you a method for tweaking just the blocks you need with ECO compilation speedup of 5x – 10x.3

Fractal Synthesis

To meet the growing need for utilizing the flexibility of an FPGA for arithmetic acceleration, Intel is introducing Fractal Synthesis - a feature that enables Intel® Quartus® Prime Design Software to use FPGA resources in a highly efficient manner for arithmetic heavy designs with repeating dot product structures. Fractal Synthesis allows users to see an up to 25% TOPS improvement compared to regular Intel® Quartus® Prime flow.4 Check out Fractal Synthesis in action with this video.

Illuminating Reports

  • New Logic Depth report showing the levels of logic for each clock domain.
  • New Neighbor Paths report showing paths before and after, the elements along these paths, and information about the slack, skew, delay, etc.
  • 3D visualization in Global Signal Visualization report to aid in analyzing clock sector and clock routing usage and congestion.
  • Global Router Congestion Analysis Reports that enable users to see a detailed view of which nets contribute to routing congestion and help users debug routing issues earlier in the compile flow. Learn how to use the new global router congestion reports with the provided video.

Documentation and Support

Find technical documentation, videos, and training courses for Intel® Quartus®
Prime Design Software.

產品與效能資訊

1

此一比較是根據 Intel® Agilex™ FPGA 和 SoC 系列相較於 Intel® Stratix® 10 FPGA 的模擬結果,其內容可能隨時變更。本文件包含在研發階段的產品、服務及/或程序之資訊。此處提供的所有資訊可能變更,恕不另行通知。請聯絡 Intel 代表以取得最新的預測、時間表、產品規格與藍圖。
Intel® 技術的功能與優勢取決於系統配置,而且可能需要支援的硬體、軟體或服務啟動才能使用。若想進一步瞭解,請前往 https://www.intel.com.tw,或洽 OEM 或零售商。沒有電腦系統能提供絕對的安全性。效能測試中使用的軟體與工作負載可能僅針對 Intel® 微處理器進行最佳化。

2

針對採用 Linux 64 作業系統的 Intel® Stratix® 10 1S280 裝置,對一套 80 位客戶的設計進行了效能標竿測試。任何有關上述條件的變更均可能導致不同結果。考慮購買時,為了充分評估效能,請參考其他資訊來源。如需更完整的效能與效能標竿評測結果相關資訊,請參閱 https://www.intel.com.tw/benchmarks

3

針對採用 Linux 64 作業系統的 Intel® Stratix® 10 1S280 裝置,為總計 28 種設計進行效能標竿測試。在網路清單變更後,對基準編譯時間與 ECO 編譯時間進行比較(8-2000,取決於 ECO 變更可採用的數值)。 效能測試等均使用特定的電腦系統、組件、軟體、作業及功能。任何有關上述條件的變更均可能導致不同結果。考慮購買時,為了充分評估效能,請參考其他資訊來源。如需有關效能與效能標竿結果的一般資訊,請參閱 http://www.intel.com.tw/benchmarks

4

針對採用 Linux 64 作業系統的 Intel® Stratix® 10 1S280 裝置,對一套 40 位客戶的設計進行了效能標竿測試。對有啟用和未啟用 Intel® Quartus® Prime Pro Edition Software v19 的 Fractal Synthesis 進行比較。1 硬體、軟體或組態上的差異將會影響實際效能。考慮購買時,為了充分評估效能,請參考其他資訊來源。如需有關效能與效能標竿測試結果的詳細資訊,請參閱 https://www.intel.com.tw/benchmarks​​​​