Nios II Stratix II 2S60 ROHS 範例的 Quartus II 編譯警告

如果您嘗試編譯Nios II Stratix ^{II 2S60 ROHS 範例設計，安裝于 EDS 安裝路徑>/範例/vhdl/niosII_stratixII_2s60/標準，或是從FPGA Wiki 下載，您可能會看到下列警告}

Warning (10541): VHDL Signal Declaration warning at NiosII_stratixII_2s60_standard.vhd(59): used implicit default value for signal "cpu_data_master_read_data_valid_NiosII_stratixII_2s60_standard_clock_0_in" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(340): used initial value expression for variable "arg_copy" because variable was never assigned a value Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(344): used initial value expression for variable "arg_length" because variable was never assigned a value

您可以安全地忽略這些警告。

Nios II Stratix II 2S60 ROHS 範例已棄用。

沒有。