重大問題
描述
在 Aldec® Riviera-PRO™ Advanced 中模擬設計時 驗證平臺，Avalon®串流 （Avalon-ST） 介面匯流排 功能模型 （BFM） 因下列錯誤而失敗：
Error: "# sim_run" not found in "log.txt". Simulation did not run.Error: Found 3 error(s) in "log.txt":
Error: 1211 | # ACOM: Error: ELAB1_0021: /build/arc/execute/dir_21768/_0/regtest/ip/merlin/altera_merlin_apb_slave_agent/sim_script/vhdl/riviera/top_tb/submodules/altera_avalon_st_sink_bfm_vhdl.vhd
: (113, 0): Types do not match for port "data_in0".
Error: 1212 | # ACOM: Error: ELAB1_0021: /build/arc/execute/dir_21768/_0/regtest/ip/merlin/altera_merlin_apb_slave_agent/sim_script/vhdl/riviera/top_tb/submodules/altera_avalon_st_sink_bfm_vhdl.vhd
: (113, 0): Types do not match for port "data_out0".
Error: 1214 | # SCRIPTER: Error: /build/arc/execute/dir_21768/_0/regtest/ip/merlin/altera_merlin_apb_slave_agent/sim_script/vhdl/riviera/aldec/rivierapro_setup.tcl
: (222, 1): Script execution terminated due to error(s).
解決方法
此問題已在 Riviera-PRO 版本 2013.06 和 13.1 Quartus® II 軟體版本。
若要在 13.0 Quartus II 軟體版本中解決這個問題， 您必須編輯您的 HDL 代碼如下 （Italics 的修改）：
entity altera_avalon_interrupt_sink_vhdl is
end altera_avalon_interrupt_sink_vhdl;
architecture irq_sink_bfm_vhdl_a of altera_avalon_interrupt_sink_vhdl is
-- component altera_avalon_interrupt_sink_vhdl_wrapper
-- port ( data_out0 : out integer );
-- end component;
component altera_avalon_interrupt_sink_vhdl_wrapper
port ( data_out0 : out std_logic_vector(0 to 31 ) );
end component;
signal data_out0 : integer;
function aldec_slv2int (val:std_logic_vector) return integer is
begin return to_integer(unsigned(val));
end aldec_slv2int;
begin
irq_sink_vhdl_wrapper : altera_avalon_interrupt_sink_vhdl_wrapper
port map ( aldec_slv2int(data_out0) => data_out0 );
end irq_sink_bfm_vhdl_a;