此範例在 Verilog HDL 中實作計時雙向針腳。OOE 的價值決定了托比爾是輸入、以吋輸入或是三狀態,將價值推出 b。
如需在專案中使用此範例的詳細資訊,請前往:
bidir.v
module bidirec (oe, clk, inp, outp, bidir);
// Port Declaration
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8'bZ ;
assign outp = b;
// Always Construct
always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end
endmodule