您將學習如何使用 Quartus® Prime Pro 軟體 22.1 版中的時序分析器約束和分析時序設計。這包括編寫 Synopsys* 設計約束 (SDC) 檔案,在時序分析器中生成各種時序報告,並將這些知識應用於FPGA設計。除了了解確保設計符合時序的基本要求外,您還將瞭解時序分析器如何説明您輕鬆創建時序約束,以説明您滿足這些要求。
注意:雖然本課程的重點是 Quartus Prime Pro 軟體,但大部分流程和約束對於該軟體的標準版和精簡版都有效。
In this class, you will work hands-on labs on a virtual machine to practice your timing analysis skills. Come as you are to the class, no setup is needed. Prior knowledge of timing analysis concepts is required. If you need to learn those, before coming to class, attend the Timing Analysis: Lecture class. There will be a brief review of the SDC constraints starting the labs.