由於 Quartus Prime® 軟體版本 16.1.2 和更早版本的問題，您的Arria® 10 SerialLite™ III 核心可能會在以下類型之「pld_10g_tx_pempty_reg節點」和「Altera 標準同步器stdsync_txpempty|din_s1」之間的路徑中出現設定計時違規問題：
從節點： seriallite_iii_streaming：seriallite_iii_streaming_inst|seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa：seriallite_iii_streaming|interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q：A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q：DUPLEX_WRAPPER.interlaken_inst|seriallite_iii_streaming_altera_xcvr_native_a10_161_koe2tsa：native_ilk_wrapper|twentynm_xcvr_native：g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5es：twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5es：inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_20nm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg
至節點： seriallite_iii_streaming：seriallite_iii_streaming_inst|seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa：seriallite_iii_streaming|interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q：A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut：pcs_lanes[5].stdsync_txpempty|din_s1
啟動頻率： seriallite_iii_streaming_inst|seriallite_iii_streaming|g_xcvr_native_insts[*]|tx_pma_clk
閂鎖頻率： seriallite_iii_streaming_inst|seriallite_iii_streaming|g_xcvr_native_insts[0]|tx_pma_clk
若要解決這個問題，使用者必須修改所產生的 ip.sdc 檔案 （seriallite_iii_streaming*.sdc）。
如下所示的原始 .sdc 限制：
set_max_skew-從 [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg]-到 [get_keepers {*$module_name*|interlaken_native_wrapper_duplex|stdsync_txpempty|din_s1[] -get_skew_value_from_clock_period src_clock_period-skew_value_multiplier 0.85
set_net_delay───從 [get_keepers{*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native：g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4：twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4：inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_20nm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg[]-到 [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*：A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut：pcs_lanes[*].stdsync_txpempty|din_s1]-最大 -get_value_from_clock_period dst_clock_period -value_multiplier 0.85
set_max_delay───從[get_keepers{*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native：g_xcvr_native_insts[[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4：twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4：inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs inst_20nm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg[]-到 [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*：A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut：pcs_lanes[*].stdsync_txpempty|din_s1[] 100
set_min_delay──從 [get_keepers{*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native：g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4：twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4：inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_20nm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg[]-到 [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*：A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut：pcs_lanes[*].stdsync_txpempty|din_s1[] -100
應用下列限制替換：
設定inst_xcvr_list [get_entity_instances twentynm_xcvr_native]
foreach each_xcvr_inst \$inst_xcvr_list {
如果 { [字串等於「quartus_sta」\$：TimeQuestInfo（名稱ofexecutable）] { {
set_max_skew──從 [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] - 到 [get_keepers {*stdsync_txpempty|din_s1]-get_skew_value_from_clock_period src_clock_period-skew_value_multiplier 0.85
}
set_net_delay────從 [get_keepers\$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -到 [get_keepers {*stdsync_txpempty|din_s1]-max -get_value_from_clock_period dst_clock_period-value_multiplier 0.85
set_max_delay──從 [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -到 [get_keepers {*stdsync_txpempty|din_s1]100
set_min_delay───從 [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -到 [get_keepers {*stdsync_txpempty|din_s1]-100
}
這個問題已經從 Quartus Prime® 軟體的軟體版本 17.0 開始修復。